SEMICONDUCTOR DEVICE AND PLL CIRCUIT

• US 20170250692A1
• Filed: 02/24/2017
• Published: 08/31/2017
• Est. Priority Date: 02/26/2016
• Status: Active Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: MOTOZAWA, Atsushi, HIRAI, Yoshitaka
• Granted Patent: US 10,291,238 B2
• Time in Patent Office: Days
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03M 1/742 using current sources as quantisation value generators

Abstract

An object is to improve Power Supply Rejection Ratio in a PLL circuit. A proportional path 103 is provided in a first power supply system 101 and outputs analog proportional signal AP according to a detection signal DET. An integral path 104 is provided in a second power supply system and outputs an analog integral signal AI according to the DET. A CCO driver 16 is provided in the first power supply system 101 and outputs control current ICCO according to the AP and the AI. A CCO 17 is provided in the second power supply system 102 and outputs an output signal Fout according to the ICCO. A phase frequency detector 11 is provided in the second power supply system 102 and configured to detect a phase difference between a reference signal Fref and a signal FM obtained by feeding back the Fout and then outputs the DET.

Claims

1. A semiconductor device comprising a phase locked loop circuit, wherein the phase locked loop circuit comprises:

a proportional path provided in a first power supply system and configured to output an analog proportional signal according to a detection signal, the detection signal indicating a phase difference between a reference signal and a signal obtained by feeding back an output signal of the phase locked loop circuit;

an integral path provided in a second power supply system and configured to output an analog integral signal according to the detection signal, a voltage of the second power supply system being lower than that of the first power supply system;

a current-controlled oscillator driver provided in the first power supply system and configured to output control current according to the analog proportional signal from the proportional path and the analog integral signal from the integral path;

a current-controlled oscillator provided in the second power supply system and configured to output an output signal generated by performing an oscillation operation according to the control current; and

a phase frequency detector provided in the second power supply system and configured to detect a phase difference between the reference signal and the signal obtained by feeding back the output signal and then output a result of the detection as the detection signal.

2. The semiconductor device according to claim 1, further comprising a level shifter, wherein

the phase frequency detector is provided in the second power supply system,

the reference signal is supplied through the second power supply system, and

the level shifter shifts a voltage level of the detection signal output by the phase frequency detector to a voltage level of the first power supply system and then outputs the shifted detection signal to the proportional path.

3. The semiconductor device according to claim 1, further comprising:

first and second phase frequency detectors, the first and second phase frequency detectors being the phase frequency detectors; and

a level shifter, wherein

the first phase frequency detector is provided in the second power supply system,

the second phase frequency detector is provided in the first power supply system,

the reference signal is supplied through the second power supply system,

the level shifter shifts a voltage level of the reference signal and a voltage level of the signal obtained by feeding back the output signal to a voltage level of the first power supply system and then outputs the shifted reference signal and the shifted output signal to the second phase frequency detector, and

the second phase frequency detector detects a phase difference between the reference signal level and the signal obtained by feeding back the output signal which are shifted by the level shifter and then outputs a result of the detection to the proportional path as the detection signal.

4. The semiconductor device according to claim 1, wherein

the integral path comprises:

a digital signal processing unit configured to perform digital processing on the detection signal and then output first and second digital integral signals;

a first digital to analog converter configured to convert the first digital integral signal into a first analog integral signal; and

a second digital to analog converter configured to convert the second digital integral signal into a second analog integral signal, wherein

the current-controlled oscillator driver adds third current obtained by duplicating first current, which is the first analog integral signal, by a predetermined ratio, fourth current obtained by duplicating second current, which is the second analog integral signal, by a predetermined ratio, and current of the analog proportional signal in order to generate the control current, and

the first current is greater than the second current.

5. The semiconductor device according to claim 4, wherein the current-controlled oscillator driver comprises:

a first current mirror configured to generate the third current by duplicating the first current by the predetermined ratio; and

a second current mirror configured to generate the fourth current by duplicating the second current by the predetermined ratio.

6. The semiconductor device according to claim 4, wherein the digital signal processing unit controls the current-controlled oscillator driver in such a way that a current ratio of the first current to the second current will become constant.

7. The semiconductor device according to claim 6, wherein

when there are variations in the first current and the first current is increased,

the current-controlled oscillator driver reduces the second current according to the increase in the first current,

the digital signal processing unit changes a value of the second digital integral signal from a first value, which is a value before the second current varies, to a second value in order to reduce the second current,

the digital signal processing unit reduces a value of the first digital integral signal in order to reduce the first current, and

the digital signal processing unit returns the value of the second digital integral signal from the second value to the first value in order to increase the second current, and

when there are variations in the first current and the first current is reduced,

the current-controlled oscillator driver increases the second current according to the reduction in the first current,

the digital signal processing unit changes the value of the second digital integral signal from the first value, which is the value before the second current varies, to the second value in order to increase the second current,

the digital signal processing unit increases the value of the first digital integral signal in order to increase the first current, and

the digital signal processing unit returns the value of the second digital integral signal from the second value to the first value in order to reduce the second current.

8. The semiconductor device according to claim 7, wherein

the first digital to analog converter includes a plurality of constant current cells that are connected in parallel and is configured to be capable of controlling the number of the constant current cells that output current according to the value of the first digital integral signal,

the second digital to analog converter includes a plurality of variable current cells that are connected in parallel and is configured to be capable of controlling the number of the variable current cells that output current according to the value of the second digital integral signal, and

the current output by each of the plurality of variable current cells is controlled in such a way that it is reduced when the first current is increased due to the variations, while the current output by each of the plurality of variable current cells is controlled in such a way that it is increased when the first current is reduced due to the variations.

9. The semiconductor device according to claim 8, further comprising a control signal generation unit configured to generate a control signal based on fifth current and control the current output by each of the plurality of variable current cells by the control signal, the fifth current being obtained by duplicating the third current from the first current by a predetermined ratio.

10. The semiconductor device according to claim 8, further comprising a bias voltage generation circuit configured to supply a bias voltage to the plurality of constant current cells.

11. The semiconductor device according to claim 4, further comprising:

a first filter inserted between the first digital to analog converter and the current-controlled oscillator driver; and

a second filter inserted between the second digital to analog converter and the current-controlled oscillator driver;

12. The semiconductor device according to claim 5, wherein the current-controlled oscillator driver comprises:

a first degeneration resistor inserted between a power supply of the first power supply system and the first current mirror, the power supply supplying power to the first current mirror; and

a second degeneration resistor inserted between the power supply of the first power supply system and the first current mirror, the power supply supplying power to the second current mirror.