ELECTROMAGNETIC JAMMING DEVICE AND METHOD FOR AN INTEGRATED CIRCUIT

• US 20170250795A1
• Filed: 07/28/2016
• Published: 08/31/2017
• Est. Priority Date: 02/25/2016
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Ordas, Thomas, Sarafianos, Alexandre, Chesnais, Stephane, Marinet, Fabrice
• Granted Patent: US 10,148,421 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06K 19/07336 Active means, e.g. jamming or scrambling of the electromagnetic field
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
• CPC Class Codes: H03K 5/01 Shaping pulses discrimination against noise or interference H03K5/125
• CPC Class Codes: H04K 2203/32 including a particular configuration of antennas
• CPC Class Codes: H04K 3/40 Jamming having variable characteristics
• CPC Class Codes: H04K 3/825 by jamming
• CPC Class Codes: H04K 3/94 related to allowing or preventing testing or assessing
• CPC Class Codes: H04L 2209/08 Randomization, e.g. dummy operations or using noise
• CPC Class Codes: H04L 2209/805 Lightweight hardware, e.g. radio-frequency identification [RFID] or sensor
• CPC Class Codes: H04L 9/002 Countermeasures against attacks on cryptographic mechanisms network architectures or network communication protocols for protection against malicious traffic H04L63/1441
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: Y04S 40/20 Information technology specific aspects, e.g. CAD, simulation, modelling, system security

Abstract

A device is provided for jamming electromagnetic radiation liable to be emitted by at least one portion of an interconnect region located above at least one zone of an integrated electronic circuit produced in and on a semiconductor substrate. The device includes an antenna located above the at least one zone of the circuit and generating circuit coupled to the antenna and configured to generate an electrical signal having at least one pseudo-random property to pass through the antenna.

Claims

1. A method for jamming electromagnetic radiation emitted by a portion of an interconnect region located above at least one zone of an integrated electronic circuit produced in and on a semiconductor substrate, comprising:

driving at least one metal antenna located above said at least one zone of the integrated circuit with an electrical signal having at least one pseudo-random property, said electrical signal passing through said at least one antenna.

2. The method according to claim 1, wherein driving comprises:

generating a clock signal,

applying pseudo-randomly a delay to at least some edges of said clock signal so as to produce said electrical signal, and

transmitting said electrical signal through the antenna (5).

3. The method according to claim 2, wherein the delay is one of a fixed delay and a variable delay.

4. The method according to claim 3, wherein the variable delay is a pseudo-randomly varying delay.

5. The method according to claim 1, wherein the at least one metal antenna comprises a first antenna and a second antenna that are placed above said at least one zone of the integrated circuit, the method further comprising:

selecting one of the first and second antennae, and

passing said electrical signal through the selected antenna.

6. A device, comprising:

an integrated electronic circuit produced in and on a semiconductor substrate;

an interconnect region located above the semiconductor substrate;

at least one antenna located within the interconnect region above at least one zone of the integrated electronic circuit; and

a generating circuit coupled to said at least one antenna and configured to generate an electrical signal having at least one pseudo-random property, said electrical signal passing through said at least one antenna in order to jam electromagnetic radiation liable to be emitted by at least one portion of the interconnect region located above at least one zone of the integrated electronic circuit.

7. The device according to claim 6, wherein the generating circuit comprises:

a clock generator configured to generate a clock signal;

a delay circuit configured to apply pseudo-randomly a delay to at least some edges of said clock signal to produce said electrical signal.

8. The device according to claim 7, wherein the delay circuit is configured to apply pseudo-randomly one of a fixed delay and a variable delay to at least some edges of said clock signal.

9. The device according to claim 8, wherein the variable delay is a pseudo-randomly varying delay.

10. The device according to claim 6, wherein the interconnect region comprises a plurality of metallization levels including at least one metallization level having a metal track forming at least part of said at least one antenna.

11. The device according to claim 6, wherein said at least one antenna comprises a first antenna and a second antenna, further comprising a selecting circuit configured to select at least one of said first and second antennae and deliver said electrical signal to the selected antenna.

12. The device according to claim 11, wherein the first antenna and the second antenna are located in a same metallization level of the interconnect region.

13. The device according to claim 11, wherein the first antenna and second antenna are located in different metallization levels of the interconnect region.

14. The device according to claim 10, wherein the first antenna is located above a first zone of the integrated circuit and said second antenna is located above a second zone of the integrated circuit.

15. The device according to claim 14, wherein the first and second zones at least partially overlap.

16. The device according to claim 14, wherein the first and second zones do not overlap.

17. The device according to claim 11, wherein the selecting circuit comprises a control register and logic gates coupled between said antennae and said control register, said control register configured to control operation of the logic gates to selectively pass the electrical signal.

18. A device, comprising:

a semiconductor substrate;

a cryptographic integrated circuit including circuit devices formed in and on said semiconductor substrate;

an interconnect region located above the semiconductor substrate, said interconnect region including metallization levels with metal lines interconnecting the circuit devices of the cryptographic integrated circuit;

an antenna located within a metallization level of the interconnect region at a position above a zone of the integrated electronic circuit wherein the circuit devices of the cryptographic integrated circuit; and

a generating circuit coupled to said at least one antenna and configured to generate an electrical signal having at least one pseudo-random property, said electrical signal passing through said antenna to produce pseudo-random electromagnetic signals in order to inhibit detection of cryptographic electromagnetic signals emitted by the metal lines interconnecting the circuit devices of the cryptographic integrated circuit.

19. The device of claim 18, wherein the generating circuit comprises:

a clock generator configured to generate a clock signal;

a delay circuit configured to apply a pseudo-random delay to edges of the clock signal in order to generate said electrical signal.