ALIGNMENT TESTING FOR TIERED SEMICONDUCTOR STRUCTURE

• US 20170254849A1
• Filed: 05/22/2017
• Published: 09/07/2017
• Est. Priority Date: 10/25/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WANG, Mill-Jer, Peng, Ching-Nen, Lin, Hung-Chih, Chen, Hao, Lee, Mincent
• Granted Patent: US 10,073,135 B2
• Time in Patent Office: Days
• CPC Class Codes: G01B 2210/56 Measuring geometric parameters of semiconductor structures, e.g. profile, critical dimensions or trench depth
• CPC Class Codes: G01B 7/12 for measuring diameters
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2891 related to sensing or controlling of force, position, temperature G01R31/2874 takes precedence; sensing of force G01L; sensing of position G01B, G01D; sensing of temperature G01K; controlling in general G05
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: G01R 31/54 Testing for continuity
• CPC Class Codes: G01R 31/66 Testing of connections, e.g. of plugs or non-disconnectable joints testing for incorrect line connections G01R31/55

Abstract

Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.

Claims

1. A method for evaluating a tiered semiconductor structure, comprising:

evaluating connectivity, through a conductive arc within a first layer of a tiered semiconductor structure, between a first via, a second via, and a third via of a second layer of the tiered semiconductor structure to determine an alignment rotation;

evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation; and

invoking at least one of a testing unit, a repair unit, or a fault tolerance unit to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure.

2. The method of claim 1, the evaluating connectivity comprising:

transmitting a first test signal through the first via and measuring a response at the second via and the third via to yield first results.

3. The method of claim 2, the evaluating connectivity comprising:

transmitting a second test signal through the third via and measuring a response at the first via and the second via to yield second results, wherein the second via is disposed between the first via and the third via.

4. The method of claim 3, the evaluating connectivity comprising:

determining the alignment rotation using the first results and the second results.

5. The method of claim 1, comprising:

forming the conductive arc in the first layer, wherein the conductive arc comprises a first arc segment having a first end and a second end, wherein the first end is separated from the second end by a second arc segment that is non-conductive; and

forming the first via, the second via, and the third via within the second layer and arranged along a third arc segment spanning from the first via to the third via and having a length equal to a length of the second arc segment, wherein;

the second via is disposed between the first via and the third via,

when the first layer is aligned with the second layer, the first via contacts the first end of the conductive arc and the third via contacts the second end of the conductive arc.

6. The method of claim 5, wherein the second via is in contact with the second arc segment when the tiered semiconductor structure is aligned.

7. The method of claim 5, wherein the first via, the second via, and the third via are evenly spaced along the third arc segment.

8. The method of claim 5, wherein:

the evaluating connectivity comprises;

transmitting a first test signal through the first via and measuring a response at the second via and the third via to yield first results;

transmitting a second test signal through the second via and measuring a response at the first via and the third via to yield second results; and

determining the alignment rotation using the first results and the second results, and

evaluating the tiered semiconductor structure for misalignment comprises;

determining whether the second layer is misaligned with the first layer based upon the alignment rotation.

9. A method for evaluating a tiered semiconductor structure, comprising:

evaluating connectivity within a first arc segment of a conductive arc, wherein the conductive arc is within a first layer of a tiered semiconductor structure and the connectivity is evaluated between a set of vias within a second layer of the tiered semiconductor structure;

responsive to determining that a first via of the set of vias has connectivity through the first arc segment to a second via of the set of vias adjacent to the first via and that the first via does not have connectivity to a third via of the set of vias adjacent to the second via, determining a counterclockwise alignment rotation;

evaluating the tiered semiconductor structure for misalignment based upon the counterclockwise alignment rotation; and

invoking at least one of a testing unit, a repair unit, or a fault tolerance unit to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure.

10. The method of claim 9, comprising:

forming the conductive arc in the first layer, wherein the first arc segment has a first end separated from a second end.

11. The method of claim 10, wherein a second arc segment that is non-conductive is disposed between first end and the second end.

12. The method of claim 11, comprising forming the set of vias, comprising:

forming the first via, the second via, and the third via within the second layer and arranged along a third arc segment spanning from the first via to the third via, wherein a length of the second arc segment is equal to a length of the third arc segment such that when the tiered semiconductor structure is aligned, the first via contacts the first end of the conductive arc and the third via contacts the second end of the conductive arc.

13. The method of claim 9, the evaluating connectivity comprising,

transmitting a first test signal through the first via and measuring a response at the second via and the third via to yield first results.

14. The method of claim 13, wherein the determining that a first via of the set of vias has connectivity through the first arc segment to a second via of the set of vias adjacent to the first via and that the first via does not have connectivity to a third via of the set of vias adjacent to the second via comprises:

determining that the first test signal was transmitted through the first via and the first arc segment to the second via; and

determining that the first test signal was not transmitted to the third via.

15. A method for evaluating a tiered semiconductor structure, comprising:

evaluating connectivity within a first arc segment of a conductive arc, wherein the conductive arc is within a first layer of a tiered semiconductor structure and the connectivity is evaluated between a set of vias within a second layer of the tiered semiconductor structure;

responsive to determining that a third via of the set of vias has connectivity through the first arc segment to a second via of the set of vias adjacent to the third via and that a first via of the set of vias does not have connectivity to the third via, determining a clockwise alignment rotation value;

evaluating the tiered semiconductor structure for misalignment based upon the clockwise alignment rotation value; and

invoking at least one of a testing unit, a repair unit, or a fault tolerance unit to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure.

16. The method of claim 15, the evaluating connectivity comprising,

transmitting a first test signal through the third via and measuring a response at the first via and the second via to yield first results.

17. The method of claim 16, wherein the determining that a third via of the set of vias has connectivity through the first arc segment to a second via of the set of vias adjacent to the third via and that a first via of the set of vias does not have connectivity to the third via comprises:

determining that the first test signal was transmitted through the third via and the first arc segment to the second via; and

determining that the first test signal was not transmitted to the first via.

18. The method of claim 15, comprising:

forming the conductive arc in the first layer, wherein the first arc segment has a first end separated from a second end.

19. The method of claim 15, comprising forming the set of vias, comprising:

forming the set of vias within the second layer and arranged along a second arc segment spanning from the first via to the third via, wherein a length of the second arc segment is equal to a length of the third arc segment.

20. The method of claim 19, wherein the set of vias are evenly spaced along the third arc segment between the first via and the third via.