TFT SUBSTRATES AND THE MANUFACTURING METHODS THEREOF

• US 20170255044A1
• Filed: 09/30/2015
• Published: 09/07/2017
• Est. Priority Date: 09/28/2015
• Status: Abandoned Application

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: GE, Shimin
• Application Number:
  US14/786,110
• Publication Number:
  US 20170255044A1
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2202/10 semiconductor
• CPC Class Codes: H01L 21/027 Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 photographic masks or originals per se G03F1/00; registration or positioning of photographic masks or originals G03F9/00; photographic cameras G03B; control of position G05D3/00
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A TFT array substrate and the manufacturing method are disclosed, one masking process is adopted to etch the first metal oxide semiconductor layer to be the first semiconductor pattern and the second semiconductor pattern. Afterward, a doping process is applied to the first semiconductor pattern and the second semiconductor pattern. Two ends of the first semiconductor pattern are processed to be a first conductor pattern and a second conductor pattern spaced apart from each other. In addition, the second semiconductor pattern is processed to be a common electrode. The remaining first semiconductor pattern is above the bottom gate electrode. In this way, the number of masking processes adopted during the manufacturing process of the array substrate is decreased, such that the manufacturing efficiency is enhanced and the manufacturing cost is reduced.

Claims

1. A manufacturing method of TFT array substrates, comprising:

providing a substrate;

forming a first metallic layer on the substrate, and etching the first metallic layer by a first masking process to be a bottom gate electrode;

forming a first metal oxide semiconductor layer on the substrate, and adopting a second masking process to etch the first metal oxide semiconductor layer to be a first semiconductor pattern and a second semiconductor pattern, applying a doping process to process the first semiconductor pattern to be a first conductor pattern and second conductor pattern and to process the second semiconductor pattern to be a third conductor pattern, the first conductor pattern and the second conductor pattern are spaced apart from each other, wherein remaining first semiconductor pattern is above the bottom gate electrode, and the third conductor pattern operates as a common electrode;

wherein photoresist patterns are formed on the metal oxide semiconductor layer, the photoresist patterns comprises a first photoresist pattern corresponding to the first semiconductor pattern and a second photoresist pattern corresponding to the second metal oxide semiconductor layer, a thickness of a middle area of the first photoresist patterns is larger than the thickness of two ends of the first photoresist patterns and is larger than the thickness of the second photoresist patterns;

the first photoresist patterns and the second photoresist patterns are adopted as masks to etch the metal oxide semiconductor layer to be a first semiconductor pattern and a second semiconductor pattern;

adopting a plasma treatment toward the first semiconductor pattern and the second semiconductor pattern with the mask of the first photoresist patterns and the second photoresist patterns, processing the two ends of the first semiconductor pattern to be the first conductor pattern and the second conductor pattern, and processing the second semiconductor pattern to be the third conductor pattern;

forming an etch blocking layer on the substrate, and adopting a sixth masking process to etch the etch blocking layer to form through holes on the etch blocking layer respectively above the first conductor pattern and the second conductor pattern;

forming a second metallic layer on the substrate, and adopting a third masking process to etch the second metallic layer to be a source electrode and a drain electrode, wherein the drain electrode covers the first semiconductor pattern, and the source electrode covers the second semiconductor pattern;

forming a passivation layer on the substrate, and adopting a fourth masking process to etch the passivation layer to form a through hole;

forming a second metal oxide semiconductor layer on the substrate, and adopting a fifth masking process to etch the second metal oxide semiconductor layer to form a top gate electrode and the pixel electrode, wherein the top gate electrode is above the remaining first semiconductor pattern, and at least a portion of the pixel electrode is overlapped with the common electrode, and one of the pixel electrodes electrically connects to the source electrode or the drain electrode via the through hole.

2. The manufacturing method as claimed in claim 1, wherein the metal oxide semiconductor layer is IGZO metal oxide semiconductor layer.

3. The manufacturing method as claimed in claim 1, wherein the second masking process adopts the photoresist pattern, which is one of the half-tone mask (HTM), gray-tone mask (GTM) and single slit mask (SSM).

4. The manufacturing method as claimed in claim 1, wherein the etch blocking layer is made by SiOx.

5. A manufacturing method of TFT array substrates, comprising:

providing a substrate;

forming a first metallic layer on the substrate, and etching the first metallic layer by a first masking process to be a bottom gate electrode;

forming a first metal oxide semiconductor layer on the substrate, and adopting a second masking process to etch the first metal oxide semiconductor layer to be a first semiconductor pattern and a second semiconductor pattern, applying a doping process to process the first semiconductor pattern to be a first conductor pattern and second conductor pattern and to process the second semiconductor pattern to be a third conductor pattern, the first conductor pattern and the second conductor pattern are spaced apart from each other, wherein remaining first semiconductor pattern is above the bottom gate electrode, and the third conductor pattern operates as a common electrode;

forming a second metallic layer on the substrate, and adopting a third masking process to etch the second metallic layer to be a source electrode and a drain electrode, wherein the drain electrode covers the first semiconductor pattern, and the source electrode covers the second semiconductor pattern;

forming a passivation layer on the substrate, and adopting a fourth masking process to etch the passivation layer to form a through hole; and

forming a second metal oxide semiconductor layer on the substrate, and adopting a fifth masking process to etch the second metal oxide semiconductor layer to form a top gate electrode and the pixel electrode, wherein the top gate electrode is above the remaining first semiconductor pattern, and at least a portion of the pixel electrode is overlapped with the common electrode, and one of the pixel electrodes electrically connects to the source electrode or the drain electrode via the through hole.

6. The manufacturing method as claimed in claim 5, wherein the metal oxide semiconductor layer is IGZO metal oxide semiconductor layer.

7. The manufacturing method as claimed in claim 5, wherein the step of forming a first metal oxide semiconductor layer on the substrate, adopting a second masking process to etch the first metal oxide semiconductor layer to be a first semiconductor pattern and a second semiconductor pattern, and applying a doping process to process the first semiconductor pattern further comprises:

wherein photoresist patterns are formed on the metal oxide semiconductor layer, the photoresist patterns comprises a first photoresist pattern corresponding to the first semiconductor pattern and a second photoresist pattern corresponding to the second metal oxide semiconductor layer, a thickness of a middle area of the first photoresist patterns is larger than the thickness of two ends of the first photoresist patterns and is larger than the thickness of the second photoresist patterns;

the first photoresist patterns and the second photoresist patterns are adopted as masks to etch the metal oxide semiconductor layer to be a first semiconductor pattern and a second semiconductor pattern; and

adopting a plasma treatment toward the first semiconductor pattern and the second semiconductor pattern with the mask of the first photoresist patterns and the second photoresist patterns, processing the two ends of the first semiconductor pattern to be the first conductor pattern and the second conductor pattern, and processing the second semiconductor pattern to be the third conductor pattern.

8. The manufacturing method as claimed in claim 7, wherein the second masking process adopts the photoresist pattern, which is one of the half-tone mask (HTM), gray-tone mask (GTM) and single slit mask (SSM).

9. The manufacturing method as claimed in claim 5, wherein the method further comprises a step between the step of forming a first metal oxide semiconductor layer on the substrate, adopting a second masking process to etch the first metal oxide semiconductor layer to be a first semiconductor pattern and a second semiconductor pattern, and applying a doping process to process the first semiconductor pattern and the step of forming a second metallic layer on the substrate, and adopting a third masking process to etch the second metallic layer to be a source electrode and a drain electrode, and the step comprises:

forming an etch blocking layer on the substrate, and adopting a sixth masking process to etch the etch blocking layer to form through holes on the etch blocking layer respectively above the first conductor pattern and the second conductor pattern.

10. The manufacturing method as claimed in claim 9, wherein the etch blocking layer is made by SiOx.

11. A TFT array substrate, comprising:

a substrate;

a bottom gate formed on the substrate;

a semiconductor pattern formed on the substrate, a first conductor pattern and a second conductor pattern at two ends of the semiconductor pattern, a common electrode, the first conductor pattern and the second semiconductor pattern are spaced apart from each other, and wherein the semiconductor pattern, the first conductor pattern, the second conductor pattern, and the common electrode are formed by the same metal oxide semiconductor layer.

12. The array substrate as claimed in claim 11, wherein the metal oxide semiconductor layer is IGZO metal oxide semiconductor layer.

13. The array substrate as claimed in claim 11, wherein the array substrate further comprises a drain electrode above the first conductor pattern and a source electrode above the second conductor pattern.

14. The array substrate as claimed in claim 13, wherein the array substrate further comprises an etch blocking layer being provided with through holes respectively corresponding to the first conductor pattern and the second conductor pattern, and the drain electrode and the source electrode electrically connect to the semiconductor pattern via the through holes.