EFFICIENT IMPLEMENTATION OF QUEUES AND OTHER DATA STRUCTURES USING PROCESSING NEAR MEMORY
First Claim
1. A system comprising:
- one or more memory devices;
one or more processors; and
one or more memory controllers comprising;
a first interface configured to be coupled to the one or more processors;
a second interface configured to be coupled to the one or more memory devices; and
control logic;
wherein responsive to receiving a first operation from a first processor via the first interface, the control logic is configured to;
perform a first access to metadata via the second interface, wherein the metadata corresponds to a data structure referenced by the first operation; and
perform a second access to the data structure via the second interface, wherein the second access is specified by the first operation.
1 Assignment
0 Petitions
Accused Products
Abstract
Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.
8 Citations
20 Claims
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1. A system comprising:
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one or more memory devices; one or more processors; and one or more memory controllers comprising; a first interface configured to be coupled to the one or more processors; a second interface configured to be coupled to the one or more memory devices; and control logic; wherein responsive to receiving a first operation from a first processor via the first interface, the control logic is configured to; perform a first access to metadata via the second interface, wherein the metadata corresponds to a data structure referenced by the first operation; and perform a second access to the data structure via the second interface, wherein the second access is specified by the first operation. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory controller comprising:
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a first interface configured to be coupled to one or more processors; a second interface configured to be coupled to one or more memory devices; and control logic; wherein responsive to receiving a first operation from a first processor via the first interface, the control logic is configured to; perform a first access to metadata via the second interface, wherein the metadata corresponds to a data structure referenced by the first operation; and perform a second access to the data structure via the second interface, wherein the second access is specified by the first operation. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method comprising:
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performing a first access to metadata via a second interface responsive to receiving a first operation from a first processor via a first interface, wherein the metadata corresponds to a data structure referenced by the first operation; and performing a second access to the data structure via the second interface, wherein the second access is specified by the first operation. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification