SEMICONDUCTOR ON INSULATOR STRUCTURE COMPRISING A SACRIFICIAL LAYER AND METHOD OF MANUFACTURE THEREOF

• US 20170256442A1
• Filed: 03/06/2017
• Published: 09/07/2017
• Est. Priority Date: 03/07/2016
• Status: Active Grant

• Current Assignee: GlobalWafers Co., Ltd. (Sino-American Silicon Products Incorporated)
• Original Assignee: SunEdison, Inc.
• Inventors: Kweskin, Sasha Joseph
• Granted Patent: US 10,026,642 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/67017 Apparatus for fluid treatment H01L21/67126, H01L21/6715 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer

Abstract

A method is provided for preparing a semiconductor-on-insulator structure comprising a sacrificial layer.

Claims

1. A method of preparing a multilayer structure, the method comprising:

bonding a handle semiconductor oxide layer in interfacial contact with a front surface of a single crystal semiconductor handle substrate to a donor semiconductor nitride layer in interfacial contact with a donor semiconductor oxide layer in interfacial contact with a front surface of a single crystal semiconductor donor substrate to thereby prepare a bonded structure, wherein (i) the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is the back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, a central plane between the front and back surfaces of the semiconductor donor substrate, and a bulk region between the front and back surfaces of the semiconductor donor substrate, wherein the single crystal semiconductor donor substrate comprises a cleave plane, and (ii) the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front surface and the back surface of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, and further wherein the handle semiconductor oxide layer has a wet etch rate ratio greater than 2.

2. The method of claim 1 wherein the single crystal semiconductor handle substrate comprises single crystal silicon.

3. The method of claim 1 wherein the single crystal semiconductor handle substrate comprises a single crystal silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

4. The method of claim 1 wherein the single crystal semiconductor donor substrate comprises single crystal silicon.

5. The method of claim 1 wherein the single crystal semiconductor donor substrate comprises a single crystal silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

6. The method of claim 1 further comprising selectively etching the handle semiconductor oxide layer having the wet etch rate ratio greater than 2.

7. The method of claim 1 wherein the handle semiconductor oxide layer has a wet etch rate ratio greater than 3.

8. The method of claim 7 further comprising selectively etching the handle semiconductor oxide layer having the wet etch rate ratio greater than 3.

9. The method of claim 1 wherein the handle semiconductor oxide layer has a wet etch rate ratio greater than 5.

10. The method of claim 9 further comprising selectively etching the handle semiconductor oxide layer having the wet etch rate ratio greater than 5.

11. The method of claim 1 further comprising plasma activating the handle semiconductor oxide layer in interfacial contact with a front surface of a single crystal semiconductor handle substrate prior to bonding.

12. The method of claim 1 wherein the donor semiconductor nitride layer comprises silicon nitride.

13. The method of claim 12 wherein the silicon nitride has a molar ratio of silicon to nitride of between about 0.7 and about 1.8.

14. The method of claim 12 wherein the donor semiconductor nitride layer has a thickness between about 500 angstroms and about 10,000 angstroms.

15. The method of claim 1 further comprising mechanically cleaving the bonded structure at the cleave plane of the single crystal semiconductor donor substrate to thereby prepare a cleaved structure comprising the single crystal semiconductor handle substrate, the handle semiconductor oxide layer, the donor semiconductor nitride layer, the donor semiconductor oxide layer, and a single crystal semiconductor device layer.

16. The method of claim 15 further comprising etching the cleaved structure to thereby remove the single crystal semiconductor handle substrate and the handle semiconductor oxide layer to thereby prepare a device structure comprising the donor semiconductor nitride layer, the donor semiconductor oxide layer, and the single crystal semiconductor device layer.

17. The method of claim 16 further comprising bonding the single crystal semiconductor device layer to a target substrate.