MULTI-IMPEDANCE RECTIFICATION FOR WIRELESS POWER TRANSFER

• US 20170256956A1
• Filed: 03/04/2016
• Published: 09/07/2017
• Est. Priority Date: 03/04/2016
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: IRISH, Linda Stacey, VON NOVAK, III, William Henry, GOVINDARAJ, Arvind, NGUYEN, Khoi
• Application Number:
  US15/061,585
• Publication Number:
  US 20170256956A1
• Time in Patent Office: Days
• CPC Class Codes: H02J 5/00 Circuit arrangements for transfer of electric power between ac networks and dc networks H02J3/36 takes precedence
• CPC Class Codes: H02J 50/10 using inductive coupling
• CPC Class Codes: H02J 50/12 of the resonant type
• CPC Class Codes: H02J 7/00712 the cycle being controlled or terminated in response to electric parameters
• CPC Class Codes: H02M 7/217 using semiconductor devices only
• CPC Class Codes: H02M 7/2195 the switches being synchronously commutated at the same frequency of the AC input voltage
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A multi-level rectifier is presented that is suitable for use at high frequencies, including into MHz range such as in the 6.78 MHz band used for wireless power transfer. Depending on the amplitude of the input waveform, the rectifier can be operated in different modes. For lower input levels, the rectifier acts as a voltage doubler. For higher input levels, the impedance of the rectifier can be varied based on the input level. The rectifier is a synchronous rectifier with a front section and a back section, where the impedance is varied by changing the phase of the control signal of the back section relative to that of the front section.

Claims

1. An apparatus for wirelessly receiving power and powering or charging a load, the apparatus comprising:

a receive coupler configured to generate an alternating current (AC) input voltage waveform in response to an externally generated magnetic field;

a rectifier circuit electrically connected to the receive coupler, the rectifier circuit comprising;

a first switch electrically connected between a first internal node and an input node electrically connected to the receive coupler to receive the input voltage waveform;

a second switch electrically connected between the input node and a second internal node;

a third switch electrically connected between the first internal node and a first output node;

a fourth switch electrically connected between the first output node and the second internal node;

a fifth switch electrically connected between the second internal node and ground;

a first capacitor electrically connected between the first internal node and the second internal node; and

a second capacitor electrically connected between the first output node and the load.

2. The apparatus of claim 1, wherein the apparatus further comprises a rectifier control circuit electrically connected to the first switch, the second switch, the third switch, and the fourth switch and configured to output:

a first control signal to control the first switch;

a second control signal to control the second switch, wherein the first control signal and the second control signal are non-overlapping and both have a frequency substantially equal to a frequency of the input voltage waveform;

a third control signal to control the third switch and the fifth switch; and

a fourth control signal to control the fourth switch.

3. The apparatus of claim 2, wherein the rectifier control circuit is configured to alter a phase between the third control signal and the first control signal.

4. The apparatus of claim 3, wherein the rectifier control circuit is configured to alter the phase to adjust an input impedance of the rectifier circuit to a target input impedance.

5. The apparatus of claim 3, wherein the rectifier control circuit is configured to alter the phase according to a sequence corresponding to a message detectable based on changes in impedance reflected by the receive coupler.

6. The apparatus of claim 2, wherein:

the rectifier control circuit is configured to cause the third control signal to be maintained at a high level according to a first mode and configured to cause the third control signal to have a frequency substantially equal to a frequency of the input voltage waveform according to a second mode; and

the rectifier control circuit is further configured to cause the fourth control signal to be maintained at a low level according to the first mode and configured to cause the fourth control signal to have a frequency substantially equal to a frequency of the input voltage waveform according to the second mode, wherein the third control signal and the fourth control signal are non-overlapping according to the second mode.

7. The apparatus of claim 6, wherein the rectifier control circuit is configured to operate according to the first mode in response to an amplitude of the input voltage waveform being less than a reference voltage level, and wherein the rectifier control circuit is configured to operate according to the second mode in response to an amplitude of the input voltage waveform being greater than the reference voltage level.

8. The apparatus of claim 6, wherein the first mode corresponds to a voltage doubler circuit and wherein the second mode corresponds to a mode wherein a DC output voltage at the first output node is substantially half or less than a peak to peak voltage level of the input voltage waveform.

9. The apparatus of claim 1, wherein the rectifier circuit further comprises a sixth switch electrically connected between the first internal node and a second output node.

10. A rectification apparatus, the apparatus comprising:

a rectifier circuit comprising a plurality of switches, the rectifier circuit configured to output a DC output voltage based on an AC input voltage waveform; and

a controller circuit electrically connected to the rectifier circuit and configured to;

drive the plurality of switches to cause the rectifier circuit to be configured in a first mode as a voltage doubler circuit in response to a voltage level of the input voltage waveform being below a reference voltage; and

drive the plurality of switches to cause the rectifier circuit to be configured in a second mode, different than the first mode, in response to the voltage level of the input voltage waveform being above the reference voltage.

11. The rectification apparatus of claim 10, wherein in the second mode the DC output voltage has a level that is at least one of substantially equal to a peak of the input voltage waveform or half or less than the peak to peak level of the input voltage waveform.

12. The rectification apparatus of claim 10, wherein the plurality of switches comprises a front set of switches electrically connected to receive the input voltage waveform and a back set of switches electrically connected to the front set of switches, the back set of switches configured to provide the DC output voltage.

13. The rectification apparatus of claim 12, wherein the front set of switches comprises a first switch electrically connected between a first internal node and an input node that receives the input voltage waveform and a second switch electrically connected between the input node and a second internal node, wherein the back set of switches comprises a third switch electrically connected between the first internal node and a first output node, a fourth switch electrically connected between the first output node and the second internal node, and a fifth switch electrically connected between the second internal node and ground, and wherein the rectifier circuit further comprises a first capacitor electrically connected between the first internal node and the second internal node and a second capacitor electrically connected between the first output node and a load.

14. The rectification apparatus of claim 12, wherein the controller circuit is configured to output a first set of control signals that control the front set of switches and output a second set of control signals that control the back set of switches, wherein the first set of control signals have a frequency substantially equal to the frequency of the input voltage waveform and wherein the first set of control signals are in phase with the input voltage waveform.

15. The rectification apparatus of claim 14, wherein the controller circuit is configured to cause the rectifier circuit to be in one of the first mode or the second mode by adjusting the second set of control signals.

16. The rectification apparatus of claim 14, wherein the controller circuit is configured to alter a phase between the second set of control signals and the first set of control signals.

17. The rectification apparatus of claim 16, wherein the controller circuit is configured to alter the phase to adjust an input impedance of the rectifier circuit to a target input impedance.

18. The rectification apparatus of claim 16, wherein the controller circuit is configured to alter the phase according to a sequence corresponding to a message.

19. The rectification apparatus of claim 10, further comprising a receive coupler electrically connected to the rectifier circuit and configured to wirelessly couple power via an externally generated magnetic field and generate the input voltage waveform.

20. A rectification circuit, comprising:

a control signal circuit configured to output a plurality of control signals, including a first control signal of a first clock signal, a second control signal of a second clock signal, wherein the first clock signal and the second clock signal are non-overlapping and both have a frequency substantially equal to a frequency of an input waveform, the control circuit further configured to output a third control signal and a fourth control signal;

the control signal circuit configured to cause the third control signal to be maintained at a non-clocked high level in response to an input waveform amplitude being less than a reference level and configured to cause the third control signal to be a third clock signal having a frequency substantially equal to a frequency of the input waveform in response to the input waveform amplitude being greater than the reference level;

the control signal circuit further configured to cause the fourth control signal to be maintained at a non-clocked low level in response to the input waveform amplitude being less than the reference level and configured to cause the fourth control signal to be a fourth clock signal having a frequency substantially equal to a frequency of the input waveform, wherein the third clock signal and the fourth clock signal are non-overlapping; and

a synchronous rectifier electrically connected to receive the input waveform and generate therefrom a first output voltage, including;

a) a front set of switches electrically connected to receive the input waveform, the first control signal, and the second control signal; and

b) a back set of switches electrically connected to the front set of switches, the third control signal and the fourth control signal, and configured to output the first output voltage from a first output node.

21. The rectification circuit of claim 20, wherein the control signal circuit is configured to alter a phase of the third clock signal and the fourth clock signal relative to a phase of the first clock signal.

22. The rectification circuit of claim 21, wherein the amount the phase is altered is based on the input waveform amplitude such that the phase of the first clock signal is a decreasing function of the amplitude of the input waveform.

23. The rectification circuit of claim 21, wherein the phase is altered to adjust an input impedance of the synchronous rectifier.

24. The rectification circuit of claim 20, wherein:

the front set of switches of the synchronous rectifier includes a first switch connected between a first internal node and an input node connected to receive the input waveform, and a second switch connected between the input node and a second internal node, wherein the first switch is connected to be controlled by the first control signal and the second switch is connected to be controlled by the second control signal; and

the back set of switches of the synchronous rectifier includes a third switch connected between the first internal node and the first output node, a fourth switch connected between the first output node and the second internal node, and a fifth switch connected between the second internal node and ground, wherein the third switch and the fifth switch are connected to be controlled by the third control signal and the fourth switch is connected to be controlled by the fourth control signal, and wherein the synchronous rectifier further includes a capacitor connected between the first internal node and the second internal node.

25. The rectification circuit of claim 24, wherein the back set of switches further includes a sixth switch connected between the first internal node and a second output node, wherein the sixth switch is connected to be controlled by the fourth control signal.

26. The rectification circuit of claim 20, wherein the rectification circuit is part of a receive circuit for wireless power transfer and the input waveform is received from a receive coupler of the receive circuit.

27. The rectification circuit of claim 26, wherein the receive circuit further includes a signaling controller connected to the rectification circuit, wherein the control signal circuit varies the plurality of control signals in response to the signaling controller to reverse signal through the receive coupler.

28. A method of providing a DC output voltage from an AC input voltage waveform, the method comprising:

rectifying the AC input voltage waveform to output the DC output voltage via a rectifier circuit comprising a plurality of switches;

altering one or more control signals of the plurality of switches to cause the rectifier circuit to be configured in a first mode as a voltage doubler circuit in response to a voltage level of the input voltage waveform being below a reference voltage; and

altering the one or more control signals of the plurality of switches to cause the rectifier circuit to be configured in a second mode, different than the first mode, in response to the voltage level of the input voltage waveform being above the reference voltage.

29. The method of claim 28, wherein the one or more control signals comprises a first set of control signals for a first set of the plurality of switches and a second set of controls signals for a second set of the plurality of the switches, and wherein the method further comprises further comprising altering a phase of the second set of control signals relative to a phase of the first set of control signals.

30. The method of claim 28, further comprising:

generating the input voltage waveform via a receive coupler configured to wirelessly couple power in response to an externally generated magnetic field generated by a transmitter; and

switching between the first mode and the second mode based on a sequence to cause a detectable change in a characteristic of the magnetic field for signaling to the transmitter.