Configurable Gate Array Based on Three-Dimensional Printed Memory

• US 20170257100A1
• Filed: 03/05/2017
• Published: 09/07/2017
• Est. Priority Date: 03/05/2016
• Status: Active Grant

• Current Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: ZHANG, Guobiao
• Granted Patent: US 9,948,306 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 17/10 in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/143 using laser-fusible links
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories

Abstract

The present invention discloses a configurable gate array based on three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a math function from a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the math functions in the math library.

Claims

1. A configurable computing element selectively realizing a first or second math function, comprising:

a semiconductor substrate including transistors thereon;

at least first and second three-dimensional printed memory (3D-P) arrays stacked above said semiconductor substrate, wherein said first 3D-P array stores at least a first portion of a first look-up table (LUT) for said first math function, and said second 3D-P array stores at least a second portion of a second LUT for said second math function;

at least a configurable interconnect coupling with said first and second 3D-P arrays, wherein said configurable computing element selectively realizes said first or second math function depending upon at least a configuration signal on said configurable interconnect.

2. The configurable computing element according to claim 1, wherein said first and second 3D-P arrays are placed side-by-side on said substrate.

3. The configurable computing element according to claim 1, wherein said second 3D-P array is stacked above said first 3D-P array.

4. The configurable computing element according to claim 3, wherein said second 3D-P array at least partially covers said first 3D-P array.

5. The configurable computing element according to claim 1, wherein data are recorded into said 3D-P using a printing method during manufacturing.

6. The configurable computing element according to claim 5, wherein said printing method is photo-lithography.

7. The configurable computing element according to claim 5, wherein said printing method is nano-imprint.

8. The configurable computing element according to claim 5, wherein said printing method is e-beam lithography.

9. The configurable computing element according to claim 5, wherein said printing method is DUV lithography.

10. The configurable computing element according to claim 5, wherein said printing method is laser-programming.

11. A configurable gate array realizing a complex math function, comprising:

an array of configurable computing elements comprising at least a configurable computing element, wherein said configurable computing element selectively realizes a math function from a math library;

an array of configurable logic elements comprising at least a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library;

a plurality of configurable interconnects coupling said array of configurable computing elements and said array of configurable logic elements;

wherein said configurable gate array realizes said complex math function by programming said array of configurable computing elements, said array of configurable logic elements and said plurality of configurable interconnects; and

said complex math function is a combination of the math functions from said math library.

12. The configurable gate array according to claim 11, wherein said configurable computing element comprises at least first and second three-dimensional printed memory (3D-P) arrays stacked above a semiconductor substrate, said first 3D-P array storing at least a first portion of a first look-up table (LUT) for a first math function from said math library, said second 3D-P array storing at least a second portion of a second LUT for a second math function from said math library.

13. The configurable gate array according to claim 12, wherein said first and second 3D-P arrays are placed side-by-side on said substrate.

14. The configurable gate array according to claim 12, wherein said second 3D-P array is stack above said first 3D-P array.

15. The configurable gate array according to claim 14, wherein said second 3D-P array at least partially covers said first 3D-P array.

16. The configurable gate array according to claim 12, wherein data are recorded into said 3D-P using a printing method during manufacturing.

17. The configurable gate array according to claim 11, wherein said first or second 3D-P array is stack above at least a selected one of said configurable logic elements.

18. The configurable gate array according to claim 17, wherein said first or second 3D-P array at least partially covers said selected one of said configurable logic elements.

19. The configurable gate array according to claim 11, wherein said first or second 3D-P array is stack above at least a selected one of said configurable interconnects.

20. The configurable gate array according to claim 19, wherein said first or second 3D-P array at least partially covers said selected one of said configurable interconnects.