NONVOLATILE MEMORY APPARATUS AND VERIFICATION WRITE METHOD THEREOF

• US 20170262171A1
• Filed: 09/26/2016
• Published: 09/14/2017
• Est. Priority Date: 03/14/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: CHEON, Jun Ho
• Granted Patent: US 10,402,098 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0066 Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2213/15 Current-voltage curve

Abstract

A non-volatile memory apparatus may include a program current generation circuit, a clamping circuit and a voltage generation circuit. The program current generation circuit may increase a program current based on a memory cell current flowing through a memory cell. The clamping circuit may clamp the memory cell current. The voltage generation circuit may apply a voltage corresponding to a verification-write voltage to the memory cell. Therefore, the verification-write operation may be performed to the memory cell.

Claims

1. A non-volatile memory apparatus comprising:

a voltage generation circuit coupled to a memory cell and configured to provide a voltage corresponding to a verification-write voltage to the memory cell;

a program current generation circuit configured to increase a program current based on a memory cell current flowing through the memory cell; and

a clamping circuit coupled to the voltage generation circuit and configured to clamp the memory cell current to maintain a range of the memory cell current below the program current.

2. The non-volatile memory apparatus of claim 1, further comprising a sense amplifier configured to generate a detection signal by detecting the memory cell current, wherein the program current generation circuit includes:

a program controller configured to generate a current update signal and a program end signal based on the detection signal; and

a clamping controller configured to generate a clamping control signal by increasing the program current according to the current update signal.

3. The non-volatile memory apparatus of claim 2, wherein the sense amplifier generates the detection signal having a first level when the memory cell current is greater than a threshold current value, and generates the detection signal having a second level when the memory cell current is less than the threshold current value.

4. The non-volatile memory apparatus of claim 2, wherein the program controller increases a value of the current update signal every time the program controller receives the detection signal having the first level.

5. The non-volatile memory apparatus of claim 4, wherein the program controller counts a number of the detection signal having the first level, and generates the program end signal when the number of the detection signal reaches a maximum.

6. The non-volatile memory apparatus of claim 4, wherein the program controller generates the program end signal when the value of the current update signal reaches a maximum.

7. The non-volatile memory apparatus of claim 4, wherein the program controller generates the program end signal in response to the detection signal having the second level.

8. The non-volatile memory apparatus of claim 2, wherein the clamping controller includes:

a variable current source configured to increase the program current based on the current update signal; and

a clamping control signal generator configured to generate the clamping control signal having a voltage level corresponding to an amount of the program current.

9. The non-volatile memory apparatus of claim 2, wherein the clamping circuit applies a clamping current substantially the same as the program current to the voltage generation circuit in response to the clamping control signal.

10. The non-volatile memory apparatus of claim 1, wherein the verification-write voltage has a higher voltage level than a read voltage.

11. A non-volatile memory apparatus comprising:

a clamping circuit configured to prevent a memory cell current flowing through a memory cell from exceeding a program current in response to a clamping control signal;

a voltage generation circuit configured to receive a verification-write voltage and apply a sensing voltage to the memory cell;

a sense amplifier configured to generate a detection signal by detecting the memory cell current;

a program controller configured to generate a current update signal and a program end signal based on the detection signal; and

a clamping controller configured to generate a clamping control signal by increasing the program current according to the current update signal.

12. The non-volatile memory apparatus of claim 11, wherein the program controller increases a value of the current update signal every time the program controller receives the detection signal having a first level.

13. The non-volatile memory apparatus of claim 11, wherein the program controller counts a number of the detection signal having a first level, and generates the program end signal when the number of the detection signal reaches a maximum.

14. The non-volatile memory apparatus of claim 11, wherein the program controller generates the program end signal when the value of the current update signal reaches a maximum.

15. The non-volatile memory apparatus of claim 11, wherein the program controller generates the program end signal in response to the detection signal having a second level.

16. The non-volatile memory apparatus of claim 11, wherein the clamping controller includes:

a variable current source configured to increase the program current based on the current update signal; and

a clamping control signal generator configured to generate the clamping control signal having a voltage level corresponding to an amount of the program current.

17. The non-volatile memory apparatus of claim 11, wherein the clamping circuit applies a clamping current substantially the same as the program current to the voltage generation circuit in response to the clamping control signal.

18. A verification-write method of a non-volatile memory apparatus for programming a memory cell, the method comprising:

clamping a current flowing through the memory cell to maintain a range of the current flowing through the memory cell below a program current having a predetermined amount;

performing a verification-read operation and a write operation at the same time by applying a verification-write voltage to the memory cell; and

increasing the amount of the program current based on whether a snap-back occurs.

19. The verification-write method of claim 18, further comprising ending the verification-write operation when the snap-back does not occur.

20. The verification-write method of claim 18, further comprising programming the memory cell with the program current having the increased amount when the snap-back occurs.

21. The verification-write method of claim 18, further performing repeatedly clamping the current flowing through the memory cell, performing the verification-read operation and the write operation at the same time, and increasing the amount of the program current until the snap-back does not occur.

22. The verification-write method of claim 18, wherein increasing the amount of the program current is performed gradually based on a number of iterations of performing the verification-write operation.

23. The verification-write method of claim 18, further comprising counting a number of iterations of performing the verification-write operation, wherein, if the number of iterations of performing the verification-write operation reaches a maximum, a program operation ends without performing a next verification-operation.