SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME

• US 20170262393A1
• Filed: 08/31/2016
• Published: 09/14/2017
• Est. Priority Date: 03/11/2016
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: TAKAKI, Shigeaki
• Granted Patent: US 10,049,060 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

A semiconductor device includes a processor for running a real-time operating system (RTOS). The RTOS causes the processor to update internal time during a first mode and to stop updating in a second mode. A first counter periodically transmits an interrupt signal to the processor that is coordinated with a periodic counting sequence. A second counter counts while the semiconductor device is in the second mode. A first circuit reads a first count value from the first counter at a starting time of a transition from the first to the second mode, masks the interrupt signal, and causes the second counter to start counting. A second circuit unmasks the interrupt signal from the first counter after a starting time of a transition from the second to the first mode and reads a second count value from the second counter.

Claims

1. A semiconductor device having a first operation mode and a second operation mode in which power consumption is less than in the first operation mode, the device comprising:

a processor for running a real time operating system (RTOS), the RTOS causing the processor to update an internal time in the first operation mode and to stop updating the internal time in the second operation mode;

a first counter configured to repeat a periodic counting sequence and periodically transmit an interrupt signal to the processor, the interrupt signal being coordinated with the periodic counting sequence;

a second counter configured to count while the semiconductor device is in the second operation mode;

a first circuit configured to read a first count value from the first counter at a starting time of a transition from the first operation mode to the second operation mode, to mask the interrupt signal to the processor after the starting time of the transition from the first operation mode to the second operation mode, and to cause the second counter to start counting; and

a second circuit configured to unmask the interrupt signal from the first counter after a starting time of a transition from the second operation mode to the first operation mode and to read a second count value counted by the second counter.

2. The semiconductor device according to claim 1, wherein the RTOS causes the processor to correct the internal time to account for a period of time in the second operation mode by using the first count value and the second count value.

3. The semiconductor device according to claim 1, wherein the first circuit is configured to start the reading of the first count value, the masking of the interrupt signal, and the counting of the second counter within one count increment of the first counter.

4. The semiconductor device according to claim 1, wherein the second circuit is further configured to start the unmasking of the interrupt signal and the reading of the second count value within one count increment of the first counter.

5. The semiconductor device according to claim 1, wherein, the second circuit is further configured to cause the transition from the second operation mode to the first operation mode when the second count value reaches a predetermined value.

6. The semiconductor device according to claim 5, wherein the second counter is configured to count down from an upper limit counter value and the predetermined value is zero.

7. The semiconductor device according to claim 1, wherein a resolution of the first counter is equal to a resolution of the second counter.

8. The semiconductor device according to claim 1, wherein a resolution of the first counter is different from a resolution of the second counter.

9. The semiconductor device according to claim 1, further comprising:

a real time counter outputting a clock signal to the first and second counters.

10. The semiconductor device according to claim 9, wherein the real time counter operates in accordance with an external crystal oscillator.

11. The semiconductor device according to claim 9, wherein the real time counter includes a non-crystal oscillator.

12. A method of controlling a semiconductor device having a first operation mode and a second operation mode in which power consumption is less than in the first operation mode, the method comprising:

reading, during a transition of the semiconductor device from the first operation mode to the second operation mode, a first count value from a first counter that is configured to repeat a periodic counting sequence;

masking an interrupt signal supplied by the first counter to a processor running a real-time operating system (RTOS), the interrupt signal being coordinated with the periodic counting sequence and used by the RTOS to update an internal time during the first operation mode, the masking continuing during the second operation mode;

triggering a second counter to start counting during the transition from the first operating mode to the second operating mode;

unmasking the interrupt signal during a transition from the second operation mode to the first operation mode;

reading a second count value counted by the second counter at a starting time of the transition from the second operation mode to the first operation mode; and

calculating a correction for the internal time using the first count value and the second value so as to account for an elapsed time of the second operation mode.

13. The method according to claim 12, wherein:

the reading of the first count value is caused by a first circuit,

the masking of the interrupt signal is caused by the first circuit, and

the triggering of the second counter to start counting is caused by the first circuit.

14. The method according to claim 13, wherein the first circuit causes the reading of the first count value, the masking of the interrupt signal, and the triggering of the second counter to start counting within one count increment of the first counter.

15. The method according to claim 12, wherein:

the unmasking of the interrupt signal is caused by a second circuit, and

the reading of the second count value is caused by the second circuit.

16. The method according to claim 15, wherein the second circuit causes the unmasking of the interrupt signal and the reading of the second count value within one count increment of the first counter.

17. A time management unit, comprising:

a first counter configured to repeat a periodic counting sequence of first counter values, periodically transmit a timing signal to a processor executing a real-time operating system, the timing signal being coordinated with the periodic counting sequence, and output a starting point counter value in response to a first control signal;

a second counter configured to start counting in response to the first control signal and to output an elapsed time counter value in response to a second control signal;

a first circuit configured to output the first control signal and to cause a masking of the timing signal upon receipt of a first mode transition signal indicating the processor is to be switched from a high power consumption mode to a low power consumption mode; and

a second circuit configured to output the second control signal and to cause an unmasking of the timing signal from the first counter upon receipt of a second mode transition signal indicating the processor is to be switched from the low power consumption mode to the high power consumption mode.

18. The time management unit according to claim 17, wherein an internal time of the real-time operating system is corrected to account for a total elapsed time in the low power consumption mode using the starting point counter value and the elapsed time counter value.

19. The time management circuit according to claim 17, wherein the second mode transition signal is issued when the second counter reaches a predetermined count value.

20. The time management circuit according to claim 17, wherein the first and second counters have a same resolution.