Method and Bus for Accessing Dynamic Random Access Memory

• US 20170262404A1
• Filed: 03/09/2017
• Published: 09/14/2017
• Est. Priority Date: 03/10/2016
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Liang, Jun, Liu, Hu, Zhang, Zhiqiang
• Granted Patent: US 10,452,604 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments of the present disclosure provide a method and bus for accessing a dynamic random access memory (DRAM). The embodiments include receiving an access instruction, where the access instruction includes an access address, the access address includes a physical address, and a first field and a second field that are additionally set, the first field is used to indicate an interleaving mode, the interleaving mode indicates a manner of selecting an access channel, the second field is used to indicate an interleaving granularity, and the interleaving granularity indicates a capacity of an address space corresponding to the access channel; determining, according to the first field and the second field, the access channel and an address corresponding to the access channel; and accessing the DRAM according to the access channel and the address corresponding to the access channel.

Claims

1. A method for accessing a dynamic random access memory (DRAM), comprising:

receiving an access instruction, wherein the access instruction comprises an access address, wherein the access address comprises a physical address, a first field, and a second field, wherein the first field is used to indicate an interleaving mode, wherein the interleaving mode indicates a manner of selecting an access channel, wherein the second field is used to indicate an interleaving granularity, and wherein the interleaving granularity indicates a capacity of an address space corresponding to the access channel;

determining, according to the first field and the second field, the access channel and an address corresponding to the access channel; and

accessing the DRAM according to the access channel and the address corresponding to the access channel.

2. The method according to claim 1, wherein when the first field indicates a 3+1 access channel interleaving mode, determining the access channel and the address corresponding to the access channel comprises:

determining a third field in the physical address, wherein the third field is used to instruct to access the DRAM among three access channels in an interleaving manner;

determining a fourth field in the physical address, wherein the fourth field is used to instruct to select an access channel from the three access channels;

determining a value of the fourth field according to a value of the second field;

determining, according to a preset mapping relationship between different values of the fourth field and the three access channels, a first access channel corresponding to the value of the fourth field; and

determining, according to the value of the fourth field, an address corresponding to the first access channel.

3. The method according to claim 1, wherein when a value of the first field indicates that the interleaving mode is a 3+1 access channel interleaving mode, determining the access channel and the address corresponding to the access channel comprises determining a third field in the physical address, wherein the third field is used to instruct to access the DRAM by using a single access channel.

4. The method according to claim 3, wherein the method further comprises determining, according to the third field, the single access channel and an address corresponding to the single access channel.

5. The method according to claim 1, wherein determining the access channel and an address corresponding to the access channel comprises:

determining a fifth field in the physical address when the first field indicates a double-access channel interleaving mode, wherein the fifth field is used to instruct to select an access channel combination from two access channel combinations to access the DRAM;

determining a sixth field in the physical address when a value of the fifth field instructs to access, in an interleaving manner, the DRAM by using two access channels in a first access channel combination, wherein the sixth field is used to instruct to select an access channel from the first access channel combination to access the DRAM;

determining a value of the sixth field according to a value of the second field;

determining, according to a preset correspondence between different values of the sixth field and the access channels in the first access channel combination, a second access channel corresponding to the value of the sixth field; and

determining, according to the fifth field and the sixth field, an address corresponding to the second access channel.

6. The method according to claim 1, wherein when the first field indicates a four-access channel interleaving mode, determining the access channel and an address corresponding to the access channel comprises:

determining a seventh field in the physical address, wherein the seventh field is used to instruct to select an access channel from four access channels to access the DRAM;

determining a value of the seventh field according to a value of the second field;

determining, according to a preset mapping relationship between different values of the seventh field and the four access channels, a third access channel corresponding to the value of the seventh field; and

determining, according to the seventh field, an address corresponding to the third access channel.

7. The method according to claim 1, wherein when the first field indicates that the interleaving mode is a single access channel mode, determining the access channel and an address corresponding to the access channel comprises:

determining an eighth field in the physical address, wherein the eighth field is used to instruct to select a single access channel to access the DRAM; and

determining, according to the eighth field, the selected single access channel and an address corresponding to the selected single access channel.

8. The method according to claim 1, wherein the first field comprises at least two bits, and the second field comprises at least three bits.

9. The method according to claim 1, wherein the interleaving granularity is 128 bytes.

10. The method according to claim 1, wherein the interleaving granularity is 256 bytes.

11. The method according to claim 1, wherein the interleaving granularity is 512 bytes.

12. The method according to claim 1, wherein the interleaving granularity is 1024 bytes.

13. The method according to claim 1, wherein the interleaving granularity is 2048 bytes.

14. The method according to claim 1, wherein the interleaving granularity is 4096 bytes.

19. The system of claim 1, wherein when the first field indicates a four-access channel interleaving mode, the bus is further configured to:

determine a seventh field in the physical address, wherein the seventh field is used to instruct to select an access channel from four access channels to access the DRAM;

determine a value of the seventh field according to a value of the second field;

determine, according to a preset mapping relationship between different values of the seventh field and the four access channels, a third access channel corresponding to the value of the seventh field; and

determine, according to the seventh field, an address corresponding to the third access channel.

15. A system, comprising:

a dynamic random access memory (DRAM);

a central processing unit (CPU); and

a bus coupled with the DRAM and the CPU, wherein the bus is configured to;

receive an access instruction, wherein the access instruction comprises an access address, wherein the access address comprises a physical address, a first field, and a second field, wherein the first field is used to indicate an interleaving mode, wherein the interleaving mode indicates a manner of selecting an access channel, wherein the second field is used to indicate an interleaving granularity, and wherein the interleaving granularity indicates a capacity of an address space corresponding to the access channel;

determine, according to the first field and the second field, the access channel and an address corresponding to the access channel; and

access the DRAM according to the access channel and the address corresponding to the access channel.

16. The system of claim 15, wherein when the first field indicates a 3+1 access channel interleaving mode, the bus is further configured to:

determine a third field in the physical address, wherein the third field is used to instruct to access the DRAM among three access channels in an interleaving manner;

determine a fourth field in the physical address, wherein the fourth field is used to instruct to select an access channel from the three access channels;

determine a value of the fourth field according to a value of the second field;

determine, according to a preset mapping relationship between different values of the fourth field and the three access channels, a first access channel corresponding to the value of the fourth field; and

determine, according to the value of the fourth field, an address corresponding to the first access channel.

17. The system of claim 15, wherein when a value of the first field indicates that the interleaving mode is a 3+1 access channel interleaving mode, the bus is further configured to determine a third field in the physical address, wherein the third field is used to instruct to access the DRAM by using a single access channel.

18. The system of claim 17, wherein the bus is further configured to determine, according to the third field, the single access channel and an address corresponding to the single access channel.

20. A system, comprising:

a dynamic random access memory (DRAM);

an input/output (I/O) peripheral; and

a bus coupled with the DRAM and the I/O peripheral, wherein the bus is configured to;

receive an access instruction, wherein the access instruction comprises an access address, wherein the access address comprises a physical address, a first field, and a second field, wherein the first field is used to indicate an interleaving mode, wherein the interleaving mode indicates a manner of selecting an access channel, wherein the second field is used to indicate an interleaving granularity, and wherein the interleaving granularity indicates a capacity of an address space corresponding to the access channel;

determine, according to the first field and the second field, the access channel and an address corresponding to the access channel; and

access the DRAM according to the access channel and the address corresponding to the access channel.