SEMICONDUCTOR PACKAGE ASSEMBLY

• US 20170263570A1
• Filed: 01/20/2017
• Published: 09/14/2017
• Est. Priority Date: 03/11/2016
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: LIN, Sheng-Mou, HO, Duen-Yi
• Granted Patent: US 10,679,949 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/06102 the bonding areas being at different heights
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48229 the bond pad protruding from the surface of the item
• CPC Class Codes: H01L 2224/49107 : on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06558 : the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate having a first pad and a second pad thereon. A logic die is mounted on the substrate. The logic die includes a first logic die pad coupled to the first pad. A memory die is mounted on the substrate. The memory die includes a first memory die pad. A first redistribution layer (RDL) trace has a first terminal and a second terminal. The first terminal is coupled to the first pad through the first memory die pad. The second terminal is coupled to the second pad rather than the first pad.

Claims

1. A semiconductor package assembly, comprising:

a substrate having a first pad and a second pad thereon;

a logic die mounted on the substrate, wherein the logic die comprises;

a first logic die pad coupled to the second pad; and

a memory die mounted on the substrate, wherein the memory die comprises;

a first memory die pad; and

a first redistribution layer (RDL) trace, having a first terminal and a second terminal, wherein the first terminal is coupled to the first pad through the first memory die pad, and wherein the second terminal is coupled to the second pad rather than the first pad.

2. The semiconductor package assembly as claimed in claim 1, wherein the first memory die pad and the first pad are both disposed close to a first side of the memory die.

3. The semiconductor package assembly as claimed in claim 2, wherein the first logic die pad and the second pad are disposed close to a second side of the memory die, wherein the first side is different from the second side.

4. The semiconductor package assembly as claimed in claim 1, wherein the first memory die pad is coupled to the first pad through a first conductive routing.

5. The semiconductor package assembly as claimed in claim 4, wherein the second terminal is coupled to the second pad only through a second conductive routing.

6. The semiconductor package assembly as claimed in claim 5, wherein the first logic die pad is coupled to the second pad only through a third conductive routing different from the first and second conductive routings.

7. The semiconductor package assembly as claimed in claim 1, wherein the first redistribution layer (RDL) trace is a ground trace.

8. The semiconductor package assembly as claimed in claim 1, wherein the first pad and the second pad are discrete ground pads.

9. The semiconductor package assembly as claimed in claim 1, wherein the first redistribution layer (RDL) trace is disposed at a single layered-level.

10. The semiconductor package assembly as claimed in claim 1, wherein the memory die is located directly on the logic die.

11. The semiconductor package assembly as claimed in claim 1, wherein the memory die is disposed beside the logic die.

12. The semiconductor package assembly as claimed in claim 1, wherein the memory die further comprises:

a second redistribution layer (RDL) trace, having a third terminal and a fourth terminal, wherein the third terminal is in coupled to a second memory die pad of the memory die, and the fourth terminal is coupled to a second logic die pad of the logic die.

13. The semiconductor package assembly as claimed in claim 12, wherein the second memory device pad is isolated from the first memory die pad, wherein the second logic die pad is isolated from the first logic die pad.

14. The semiconductor package assembly as claimed in claim 12, wherein the second redistribution layer (RDL) trace is not coupled to the first pad or the second pad.

15. The semiconductor package assembly as claimed in claim 12, wherein the fourth terminal is coupled to the second logic die pad through a conductive structure of the substrate.

16. The semiconductor package assembly as claimed in claim 12, wherein the second redistribution layer (RDL) trace is a signal trace.

25. The semiconductor package assembly as claimed in claim 14, wherein the memory die is located directly on the logic die.

26. The semiconductor package assembly as claimed in claim 14, wherein the memory die is disposed beside the logic die.

17. A semiconductor package assembly, comprising:

a substrate having a first pad and a second pad thereon;

a memory die having a first side and a second side and mounted on the substrate, wherein the memory die comprises;

a memory die pad close to the first side and coupled to the first pad; and

a redistribution layer (RDL) trace, having a first terminal close to the first side and a second terminal close to the second side, wherein the first terminal is coupled to the first pad through the memory die pad, and wherein the second terminal is coupled to the second pad close to the second side through a first single conductive routing; and

a logic die mounted on the substrate, wherein the logic die comprises;

a logic die pad close to the second side and coupled to the second pad.

18. The semiconductor package assembly as claimed in claim 17, wherein the first single conductive routing is not in contact with the first pad.

19. The semiconductor package assembly as claimed in claim 18, wherein the memory die pad is coupled to the first pad through a second single conductive routing that is not in contact with the first single conductive routing.

20. The semiconductor package assembly as claimed in claim 19, wherein the logic die pad is coupled to the second pad rather than the first pad.

21. The semiconductor package assembly as claimed in claim 20, wherein the logic die pad is coupled to the second pad through a third single conductive routing that is not in contact with the first and second single conductive routings.

22. The semiconductor package assembly as claimed in claim 17, wherein the redistribution layer (RDL) trace is a ground trace.

23. The semiconductor package assembly as claimed in claim 17, wherein the first pad and the second pad are discrete ground pads.

24. The semiconductor package assembly as claimed in claim 17, wherein the redistribution layer (RDL) trace is disposed at a single layered-level.

27. A semiconductor package assembly, comprising:

a substrate having a first ground pad and a second ground pad thereon;

a memory die mounted on the substrate, wherein the memory die comprises;

a memory ground pad coupled to the first ground pad; and

a redistribution layer (RDL) ground trace having a first terminal and a second terminal, wherein the first terminal is coupled to the first ground pad through a first conductive path comprising the memory ground pad, the second terminal is coupled to the second ground pad through a second conductive path that is not coupled to the memory ground pad; and

a logic die mounted on the substrate, wherein the logic die comprises a logic ground pad coupled to the second terminal through the second ground pad.

28. The semiconductor package assembly as claimed in claim 27, wherein the first ground pad and the second ground pad are discrete ground pads, wherein the first conductive path is different from the second conductive path.

29. The semiconductor package assembly as claimed in claim 27, wherein the first terminal is located close to the first ground pad and the memory ground pad.

30. The semiconductor package assembly as claimed in claim 27, wherein the second terminal is away from the first ground pad and the memory ground pad, wherein the second terminal is close to the second ground pad.

31. The semiconductor package assembly as claimed in claim 27, wherein the memory die is located directly on the logic die.

32. The semiconductor package assembly as claimed in claim 27, wherein the memory die is disposed beside the logic die.