SEMICONDUCTOR MEMORY DEVICE

• US 20170263618A1
• Filed: 03/10/2017
• Published: 09/14/2017
• Est. Priority Date: 03/10/2016
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: SHIMOJO, Yoshiro
• Granted Patent: US 9,960,173 B2
• Time in Patent Office: Days
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.

Claims

1. A semiconductor memory device, comprising:

a substrate;

a first interconnect provided on one side of the substrate in a first direction;

a second interconnect provided on the one side of the first interconnect;

a plurality of third interconnects extending in a second direction, being arranged to be separated from each other along the first direction, and being provided on the one side of the second interconnect, the second direction crossing the first direction;

a fourth interconnect provided on the one side of the third interconnects;

a semiconductor member extending in the first direction and piercing the plurality of third interconnects, one end portion of the semiconductor member being connected to the second interconnect;

a charge storage member provided between the semiconductor member and one of the plurality of third interconnects; and

a conductive member connected between the first interconnect and the fourth interconnect and insulated from the second interconnect and the plurality of third interconnects,

one of the plurality of third interconnects being disposed on two second-direction sides of the conductive member, and portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member being formed as one body.

2. The device according to claim 1, further comprising two fifth interconnects extending in the second direction, being provided between the fourth interconnect and the third interconnects, and being separated from each other in a third direction, the third direction crossing a plane including the first direction and the second direction,

the conductive member being disposed between the two fifth interconnects.

3. The device according to claim 2, further comprising two insulating members extending in the second direction, being provided between the two fifth interconnects, and being separated from each other in the second direction,

the conductive member being disposed between the two insulating members.

4. The device according to claim 1, wherein

a transistor is formed in a surface of the substrate, and

the first interconnect is connected to a source, a drain, or a gate of the transistor.

5. The device according to claim 4, wherein

a memory cell is formed between the semiconductor member and each of the third interconnects, and

the first interconnect and the transistor are a portion of a control circuit controlling the memory cells.

6. The device according to claim 1, wherein each of the plurality of third interconnects is disposed on two second-direction sides of the conductive member, and portions of the third interconnect disposed on the two second-direction sides of the conductive member are formed as one body for each of the plurality of third interconnects.

7. The device according to claim 1, wherein the semiconductor members are provided on two second-direction sides of the conductive member.

8. The device according to claim 1, wherein

the semiconductor members are provided on two third-direction sides of the conductive member, and

the third direction crosses a plane including the first direction and the second direction.

9. The device according to claim 1, wherein

the plurality of third interconnects is arranged in the first direction, and

the conductive member extends in the first direction.

10. A semiconductor memory device, comprising:

a substrate;

a plurality of first interconnects provided on one side of the substrate in a first direction;

a second interconnect provided on the one side of the first interconnects;

a plurality of third interconnects extending in a second direction, being provided on the one side of the second interconnect, and being arranged to be separated from each other along the first direction, the second direction crossing the first direction;

a plurality of fourth interconnects provided on the one side of the third interconnects;

a plurality of semiconductor members extending in the first direction and piercing the plurality of third interconnects, one end portion of the plurality of semiconductor members being connected to the second interconnect;

a charge storage member provided between one of the plurality of third interconnects and one of the plurality of semiconductor members; and

a plurality of conductive members connected between the plurality of first interconnects and the plurality of fourth interconnects and insulated from the second interconnect and the plurality of third interconnects,

one of the plurality of third interconnects being disposed on one side in a third direction when viewed from one of the plurality of conductive members, the third direction crossing a plane including the first direction and the second direction.

11. The device according to claim 10, wherein the plurality of conductive members is arranged along the second direction and the third direction.

12. The device according to claim 10, wherein two of the plurality of semiconductor members are disposed on two sides in the second direction when viewed from one of the plurality of conductive members.

13. The device according to claim 10, wherein the one of the plurality of third interconnects is disposed also on another side in the third direction when viewed from the one of the plurality of conductive members.

14. The device according to claim 10, further comprising two fifth interconnects extending in the second direction, being provided between the plurality of third interconnects and the plurality of fourth interconnects, and being separated from each other in the third direction,

one of the plurality of conductive members being disposed between the two fifth interconnects.

15. The device according to claim 14, further comprising two insulating members extending in the second direction, being provided between the two fifth interconnects, and being separated from each other in the second direction,

the one of the plurality of conductive members being disposed between the two insulating members.

16. A semiconductor memory device, comprising:

a substrate;

a first interconnect provided on one side of the substrate in a first direction;

a second interconnect provided on the one side of the first interconnect;

a plurality of third interconnects extending in a second direction, being provided on the one side of the second interconnect, and being arranged to be separated from each other along the first direction, the second direction crossing the first direction;

a fourth interconnect provided on the one side of the third interconnects;

a semiconductor member extending in the first direction and piercing the plurality of third interconnects, one end portion of the semiconductor member being connected to the second interconnect;

a charge storage member provided between the semiconductor member and one of the plurality of third interconnects; and

a conductive member connected between the first interconnect and the fourth interconnect and insulated from the second interconnect and the plurality of third interconnects,

one of the plurality of third interconnects being disposed on one side in a third direction when viewed from the conductive member, the third direction crossing a plane including the first direction and the second direction.

17. The device according to claim 16, wherein the one of the plurality of third interconnects is disposed also on another side in the third direction when viewed from the conductive member.