SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS

• US 20170263665A1
• Filed: 05/23/2017
• Published: 09/14/2017
• Est. Priority Date: 12/19/2013
• Status: Abandoned Application

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: KOMAI, Naoki, SASAKI, Naoto, OGAWA, Naoki, OINOUE, Takashi, IWAMOTO, Hayato, OOKA, Yutaka, NAGATA, Masaya
• Application Number:
  US15/603,210
• Publication Number:
  US 20170263665A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration

Abstract

A semiconductor device includes a first semiconductor substrate in which a pixel region where pixel portions performing photoelectric conversion are two-dimensionally arranged is formed and a second semiconductor substrate in which a logic circuit processing a pixel signal output from the pixel portion is formed, the first and second semiconductor substrates being laminated. A protective substrate protecting an on-chip lens is disposed on the on-chip lens in the pixel region of the first semiconductor substrate with a sealing resin interposed therebetween.

Claims

1-28. -28. (canceled)

29. A semiconductor package comprising:

a first substrate including a first semiconductor substrate having a plurality of pixels at a pixel region and a first wiring layer disposed at a side of the first semiconductor substrate;

a second substrate including a second semiconductor substrate having a logic circuit and a second wiring layer disposed at a side of the second semiconductor substrate, wherein the first and second substrates are stacked such that the first and second wiring layers are opposed to each other;

a protective substrate disposed on the first substrate with an adhesive portion interposed therebetween;

a conductor disposed at a peripheral region between an outer edge of the protective substrate and an outer edge of the pixel region, wherein the conductor is connected with a first wiring in the first wiring layer and a second wiring in the second wiring layer;

a terminal disposed at a side of the second semiconductor substrate that is opposite to the second wiring layer, wherein at least a part of the terminal is disposed at the pixel region;

a rewiring electrically connected with the terminal and a third wiring disposed at a different layer from the second wiring in the second wiring layer, wherein at least a part of the third wiring is disposed at the peripheral region, and the rewiring extends from peripheral region to the pixel region; and

an insulation film disposed between the second semiconductor substrate and the rewiring.

30. The semiconductor package according to claim 29, wherein the conductor penetrates through the first substrate.

31. The semiconductor package according to claim 30, wherein the conductor includes a first electrode portion extending from a light-incident side of the first substrate to the first wiring and a second electrode portion extending from the light-incident side of the first substrate to the second wiring.

32. The semiconductor package according to claim 29, wherein the conductor includes a first metal portion in the first wiring layer and a second metal portion in the second wiring layer, wherein the first and second metal portions are bonded by a metal bond.

33. The semiconductor package according to claim 29, further comprising a silicon through-hole electrically connected with the rewiring and the third wiring.

34. The semiconductor package according to claim 33, wherein in the silicon through-hole is between the rewiring and the third wiring.

35. The semiconductor package according to claim 33, wherein at least a portion of the silicon through-hole includes a material other than a conductor.

36. The semiconductor package according to claim 29, wherein the insulating film includes at least one of SiO2 or SiN material.

37. The semiconductor package according to claim 29, wherein the rewiring includes at least one of copper, tungsten, titanium, tantalum, a titanium tungsten alloy, or a poly silicon material.

38. The semiconductor package according to claim 29, wherein the conductor includes a first electrode portion extending from a light-incident side of the first substrate to the first wiring and a second electrode portion extending from the light-incident side of the first substrate to the second wiring, and wherein the first electrode portion and the second electrode portion are connected to one another in a region between the first wiring layer and a second insulating film disposed between the conductor and the protective substrate.

39. The semiconductor package according to claim 38, wherein a portion of the first semiconductor substrate is between a part of the first electrode portion and a part of the second electrode portion.

40. A semiconductor package comprising:

a first substrate including a first semiconductor substrate having a plurality of pixels at a pixel region and a first wiring layer disposed at a side of the first semiconductor substrate;

a second substrate including a second semiconductor substrate having a first circuit and a second wiring layer disposed at a side of the second semiconductor substrate;

a third substrate including a third semiconductor substrate having a second circuit and a third wiring layer disposed at a side of the third semiconductor substrate, wherein the first, second, and third substrates are stacked in this order;

a protective substrate disposed on the first substrate with an adhesive portion interposed therebetween;

a first conductor disposed at a peripheral region between an outer edge of the protective substrate and an outer edge of the pixel region, wherein the first conductor is electrically connected with a first wiring in the first wiring layer and a second wiring in the second wiring layer;

a second conductor disposed at the peripheral region, wherein the second conductor is connected with a third wiring in the second wiring layer and a fourth wiring in the third wiring layer;

a terminal disposed at a side of the third substrate that is opposite to the second substrate, wherein at least a part of the terminal is disposed at the pixel region; and

a rewiring electrically connected with the terminal and a fifth wiring disposed at a layer different from the fourth wiring in the third wiring layer, wherein at least a part of the fifth wiring is disposed at the peripheral region, and the rewiring extends from peripheral region to the pixel region.

41. The semiconductor package according to claim 40, wherein the first conductor penetrates through the first substrate.

42. The semiconductor package according to claim 40, wherein the first conductor includes a first electrode portion extending from a light-incident side of the first substrate to the first wiring and a second electrode portion extending from the light-incident side of the first substrate to the second wiring.

43. The semiconductor package according to claim 40, wherein the second conductor penetrates the through the second substrate.

44. The semiconductor package according to claim 43, wherein the second conductor includes a first electrode portion extending from a side of the second substrate closest to the first wiring layer to the third wiring and a second electrode portion extending from the side of the second substrate closest to the first wiring layer to the fourth wiring.

45. The semiconductor package according to claim 40, further comprising a silicon through electrode between the rewiring and the fifth wiring.

46. The semiconductor package according to claim 45, further comprising a connection wiring between the rewiring and the silicon through electrode.

47. The semiconductor package according to claim 40, wherein the first conductor includes a first electrode portion extending from a light-incident side of the first substrate to the first wiring and a second electrode portion extending from the light-incident side of the first substrate to the second wiring. and wherein the first electrode portion and the second electrode portion are connected to one another in a region between the first wiring layer and the protective substrate.

48. The semiconductor package according to claim 40, wherein the second conductor includes a first electrode portion extending from a side of the second substrate closest to the first wiring layer to the third wiring and a second electrode portion extending from the side of the second substrate closest to the first wiring layer to the fourth wiring, and wherein the first electrode portion and the second electrode portion are connected to one another in a region between the first wiring layer and the second wiring layer.

49. An imaging apparatus camera module comprising:

a semiconductor package including;

a first substrate including a first semiconductor substrate having a plurality of pixels at a pixel region and a first wiring layer disposed at a side of the first semiconductor substrate,

a second substrate including a second semiconductor substrate having a logic circuit and a second wiring layer disposed at a side of the second semiconductor substrate, wherein the first and second substrates are stacked such that the first and second wiring layers are opposed to each other,

a protective substrate disposed on the first substrate with an adhesive portion interposed therebetween,

a conductor disposed at a peripheral region between an outer edge of the protective substrate and an outer edge of the pixel region, wherein the conductor is connected with a first wiring in the first wiring layer and a second wiring in the second wiring layer,

a terminal disposed at a side of the second semiconductor substrate that is opposite to the second wiring layer, wherein at least a part of the terminal is disposed at the pixel region,

a rewiring electrically connected with the terminal and a third wiring disposed at a different layer from the second wiring in the second wiring layer, wherein at least a part of the third wiring is disposed at the peripheral region, and the rewiring extends from peripheral region to the pixel region, and

an insulation film disposed between the second semiconductor substrate and the rewiring; and

memory coupled to the semiconductor package.

50. A camera module comprising:

a semiconductor package including;

a first substrate including a first semiconductor substrate having a plurality of pixels at a pixel region and a first wiring layer disposed at a side of the first semiconductor substrate,

a second substrate including a second semiconductor substrate having a first circuit and a second wiring layer disposed at a side of the second semiconductor substrate,

a third substrate including a third semiconductor substrate having a second circuit and a third wiring layer disposed at a side of the third semiconductor substrate, wherein the first, second, and third substrates are stacked in this order,

a protective substrate disposed on the first substrate with an adhesive portion interposed therebetween,

a first conductor disposed at a peripheral region between an outer edge of the protective substrate and an outer edge of the pixel region, wherein the first conductor is electrically connected with a first wiring in the first wiring layer and a second wiring in the second wiring layer,

a second conductor disposed at the peripheral region, wherein the second conductor is connected with a third wiring in the second wiring layer and a fourth wiring in the third wiring layer,

a terminal disposed at a side of the third substrate that is opposite to the second substrate, wherein at least a part of the terminal is disposed at the pixel region, and

a rewiring electrically connected with the terminal and a fifth wiring disposed at a layer different from the fourth wiring in the third wiring layer, wherein at least a part of the fifth wiring is disposed at the peripheral region, and the rewiring extends from peripheral region to the pixel region; and

memory coupled to the semiconductor package.