Integrated Circuit Transistor Structure with High Germanium Concentration SiGe Stressor

• US 20170263749A1
• Filed: 05/19/2017
• Published: 09/14/2017
• Est. Priority Date: 07/28/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Chih-Hao, XU, Jeff J., WANG, Chien-Hsun, YEH, Chih Chieh, CHANG, Chih-Hsiang
• Granted Patent: US 10,693,003 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/18 the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials H01L21/041 - H01L21/0425, H01L21/045 - H01L21/048 take precedence
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.

Claims

1. A method for forming a transistor, said method comprising:

providing a semiconductor substrate having a source/drain region;

forming a first SiGe layer over the source/drain region;

performing a thermal oxidation to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer; and

performing a thermal diffusion process after the thermal oxidation is performed, to form a SiGe area from the second SiGe layer, wherein the SiGe area has a higher Ge concentration than the first SiGe layer.

2. The method of claim 1, wherein the providing the semiconductor substrate having the source/drain region includes:

epitaxially growing an epitaxial SiGe region, wherein the first SiGe layer is disposed on the epitaxial SiGe region.

3. The method of claim 2, further comprising:

wherein after the performing the thermal diffusion process to form the SiGe area, the SiGe area has an interface with a remaining portion of the epitaxial SiGe region.

4. The method of claim 1, wherein the providing the semiconductor substrate having the source/drain region includes:

providing the semiconductor substrate with a channel region extending from the source/drain region to under the gate, wherein the first SiGe layer is formed over the channel region.

5. The method of claim 4, wherein the first SiGe layer is formed directly interfacing the channel region.

6. The method of claim 4, further comprising:

providing a gate over a portion of the channel region, the gate having sidewall spacers.

7. The method of claim 6, wherein the SiGe area extends under the sidewall spacers.

8. The method of claim 1, wherein the providing the semiconductor substrate having the source/drain region includes:

forming a fin extending from the semiconductor substrate, wherein the source/drain region is disposed in the fin.

9. The method of claim 8, further comprising:

removing a portion of the fin in the source/drain region to form a remaining fin, wherein a top surface of the remaining fin is below an adjacent isolation structure.

10. The method of claim 9, further comprising:

growing an epitaxial SiGe film on the top surface of the remaining fin.

11. The method of claim 10, wherein the first SiGe layer is formed on the epitaxial SiGe film.

12. The method of claim 8, further comprising:

forming the first SiGe layer on a top surface and sidewalls of the fin.

13. The method of claim 12, wherein the first SiGe layer is formed over an isolation feature abutting the fin.

14. A method for forming a SiGe stressor, comprising:

depositing a first SiGe layer over a fin extending from the semiconductor substrate;

depositing a Si cap layer on the first SiGe layer;

performing a thermal oxidation to convert a top portion of the first SiGe layer and the Si cap layer to an oxide layer and to convert a bottom portion of the first SiGe layer to a second SiGe layer; and

performing a thermal diffusion process after the thermal oxidation is performed to form a SiGe stressor from the second SiGe layer, wherein the SiGe stressor has a higher Ge percentage than the first SiGe layer.

15. The method of claim 14, wherein the thermal diffusion process is separate from the thermal oxidation.

16. The method of claim 14, wherein the depositing the first SiGe layer over the fin includes depositing the first SiGe layer over a shallow trench isolation abutting the fin.

17. The method of claim 16, wherein the SiGe stressor abuts a top surface of the shallow trench isolation.

18. A method for forming a fin-type field effect transistor, comprising:

providing a fin structure extending from a substrate;

forming a first SiGe layer over a top surface and side surfaces of the fin structure;

performing a thermal oxidation to convert a top portion of the first SiGe layer to an oxide layer and to convert a bottom portion of the first SiGe layer to a second SiGe layer; and

after performing the thermal oxidation, performing a thermal diffusion to form a SiGe stressor layer, wherein the forming the SiGe stressor layer includes consuming at least a portion of the fin.

19. The method of claim 18, further comprising:

forming a Si cap layer over the first SiGe layer prior to the performing the thermal oxidation.

20. The method of claim 18, wherein the thermal oxidation is performed below 800°

Celsius.