RING OSCILLATOR CIRCUIT AND CLOCK SIGNAL GENERATION CIRCUIT

• US 20170264272A1
• Filed: 03/01/2017
• Published: 09/14/2017
• Est. Priority Date: 03/11/2016
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: HATANAKA, Koichi
• Granted Patent: US 10,320,368 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 3/00 Circuits for generating electric pulses; Monostable, bistable or multistable circuits H03K4/00 takes precedence; for digital function generators in computers G06F1/02
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 1/028 of generators comprising piezoelectric resonators H03L1/021, H03L1/022 take precedence; oscillation generators with a piezoelectric resonator H03B5/32
• CPC Class Codes: H03L 1/04 Constructional details for maintaining temperature constant
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

A ring oscillator circuit includes a plurality of first delay circuits each including X first delay elements, and a second delay circuit including a plurality of second delay elements different in delay amount from each other arranged in parallel to each other so as to be alternatively loaded, the plurality of first delay circuits and the second delay circuit are configured to be connected to each other in a ring-like manner, and X is an integer fulfilling X≧1.

Claims

1. A ring oscillator circuit comprising:

a plurality of first delay circuits each including X first delay elements; and

a second delay circuit including a plurality of second delay elements different in delay amount from each other arranged in parallel to each other so as to be alternatively loaded,

wherein the plurality of first delay circuits and the second delay circuit are configured to be connected to each other in a ring-like manner, and

X is an integer fulfilling X≧

1.

2. The ring oscillator circuit according to claim 1, wherein

the second delay circuit is singly provided.

3. The ring oscillator circuit according to claim 1, wherein

the plurality of second delay elements has respective delay amounts, which are no smaller than 1 time and no larger than 2 times of a delay amount of the first delay element, and are different from each other.

4. The ring oscillator circuit according to claim 1, wherein

the plurality of second delay elements is respectively formed of field-effect transistors different in gate length from each other.

5. The ring oscillator circuit according to claim 1, wherein

the plurality of second delay elements is respectively formed of field-effect transistors different in gate width from each other.

6. A clock signal generation circuit comprising:

the ring oscillator circuit according to claim 1; and

a control section adapted to alternatively select the second delay element to be loaded among the plurality of second delay elements in accordance with a given clock signal so that the ring oscillator circuit generates a clock signal in accordance with the given clock signal.

7. The clock signal generation circuit according to claim 6, wherein

the second delay circuit is singly provided.

8. The clock signal generation circuit according to claim 6, wherein

the plurality of second delay elements has respective delay amounts, which are no smaller than 1 time and no larger than 2 times of a delay amount of the first delay element, and are different from each other.

9. The clock signal generation circuit according to claim 6, wherein

the plurality of second delay elements is respectively formed of field-effect transistors different in gate length from each other.

10. The clock signal generation circuit according to claim 6, wherein

the plurality of second delay elements is respectively formed of field-effect transistors different in gate width from each other.