High Speed and High Voltage Driver
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Accused Products
Abstract
Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.
8 Citations
78 Claims
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1. (canceled)
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6. (canceled)
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12. A high speed high voltage (HSHV) driver comprising:
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a first stack of transistors of a first type coupled between a high voltage and an output node of the HSHV driver; a second stack of transistors of a second type opposite the first type coupled between the output node and a reference voltage; a first biasing circuit configured to provide biasing voltages to the first stack, the first biasing circuit comprising a first biasing stack of transistors of the second type; and a second biasing circuit configured to provide biasing voltages to the second stack, the second biasing circuit comprising a second biasing stack of transistors of the first type, wherein; the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage, transistors of the first stack, the second stack, the first biasing stack and the second biasing stack having desired operating voltages substantially smaller than the high voltage, transistors of each of the first stack, the first biasing stack, the second stack and the second biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor, a gate node of the first transistor of the first stack is configured to receive a level shifted version of the input signal, a gate node of the first transistor of the second stack is configured to receive the input signal, a source node of the first transistor of the first stack is coupled to the high voltage; a source node of the first transistor of the second stack is coupled to the reference voltage; a drain node of the last transistor of the first stack and a drain node of the last transistor of the second stack are coupled to the output node; gate nodes of a first to a last transistor of the first stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of a first to a last transistor of the first biasing stack, common source-drain nodes of the first to the last transistor of the first stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the first biasing stack, gate nodes of a first to a last transistor of the second stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of a first to a last transistor of the second biasing stack, common source-drain nodes of the first to the last transistor of the second stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the second biasing stack, the first biasing circuit further comprises a plurality of series connected resistors configured as a first resistive voltage divider between the high voltage coupled to the source node of the first transistor of the first stack and the output node coupled to the drain node of the last transistor of the first stack, where resistive nodes of the first resistive voltage divider connecting two consecutive resistors of the plurality of series connected resistors are coupled to the common source-drain nodes of the transistors of the first stack in a one to one relationship, and the second biasing circuit further comprises a plurality of series connected resistors configured as a second resistive voltage divider between the reference voltage coupled to the source node of the first transistor of the second stack and the output node coupled to the drain node of the last transistor of the second stack, where resistive nodes of the second resistive voltage divider connecting two consecutive resistors of the plurality of series connected resistors are coupled to the common source-drain nodes of the transistors of the second stack in a one to one relationship. - View Dependent Claims (2, 3, 4, 5, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 29, 30, 31, 32)
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25. A high speed high voltage (HSHV) driver comprising:
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a first stack of transistors of a first type coupled between a high voltage and an output node of the HSHV driver; a second stack of transistors of a second type opposite the first type coupled between the output node and a reference voltage; a first biasing circuit configured to provide biasing voltages to the first stack, the first biasing circuit comprising a first biasing stack of transistors of the second type; and a second biasing circuit configured to provide biasing voltages to the second stack, the second biasing circuit comprising a second biasing stack of transistors of the first type, wherein; the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage, transistors of the first stack, the second stack, the first biasing stack and the second biasing stack having desired operating voltages substantially smaller than the high voltage, transistors of each of the first stack, the first biasing stack, the second stack and the second biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor, a gate node of the first transistor of the first stack is configured to receive a level shifted version of the input signal, a gate node of the first transistor of the second stack is configured to receive the input signal, a source node of the first transistor of the first stack is coupled to the high voltage; a source node of the first transistor of the second stack is coupled to the reference voltage; a drain node of the last transistor of the first stack and a drain node of the last transistor of the second stack are coupled to the output node; gate nodes of a first to a last transistor of the first stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of a first to a last transistor of the first biasing stack, common source-drain nodes of the first to the last transistor of the first stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the first biasing stack, gate nodes of a first to a last transistor of the second stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of a first to a last transistor of the second biasing stack, common source-drain nodes of the first to the last transistor of the second stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the second biasing stack, the first biasing circuit further comprises a plurality of series connected resistors configured as a first resistive voltage divider between the high voltage coupled to the source node of the first transistor of the first stack and the output node coupled to the drain node of the last transistor of the first stack, where resistive nodes of the first resistive voltage divider connecting two consecutive resistors of the plurality of series connected resistors are coupled to the gate nodes of the transistors of the first stack, and the second biasing circuit further comprises a plurality of series connected resistors configured as a second resistive voltage divider between the reference voltage coupled to the source node of the first transistor of the second stack and the output node coupled to the drain node of the last transistor of the second stack, where resistive nodes of the second resistive voltage divider connecting two consecutive resistors of the plurality of series connected resistors are coupled to the gate nodes of the transistors of the second stack. - View Dependent Claims (26, 27, 28)
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33. A high speed high voltage (HSHV) driver comprising:
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a stack of transistors of a first type coupled between a reference voltage and an output node of the HSHV driver; a biasing circuit configured to provide biasing voltages to the stack, the biasing circuit comprising a biasing stack of transistors of a second type; wherein; the output node is a drain node of an output transistor of the stack of transistors adapted to be coupled to a high voltage, the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage, and transistors of the stack and the biasing stack having desired operating voltages substantially smaller than the high voltage, transistors of the stack and the biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor, the last transistor of the stack is the output transistor and the first transistor of the stack is an input transistor of the HSHV driver, a gate node of the input transistor is configured to receive the input signal, a source node of the input transistor is coupled to the reference voltage; gate nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of the first to the last transistor of the biasing stack, common source-drain nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the biasing stack, the biasing circuit further comprises a plurality of series connected resistors configured as a resistive voltage divider between the source node of the first transistor of the stack and the drain node of the last transistor of the stack, and resistive nodes of the resistive voltage divider connecting two consecutive resistors of the plurality of series connected resistors are coupled to the common source-drain nodes of the transistors of the stack in a one to one relationship. - View Dependent Claims (35, 37, 38, 39, 42, 43, 45, 46, 47, 48, 49, 50, 51, 52)
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34. A high speed high voltage (HSHV) driver comprising:
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a stack of transistors of a second type coupled between a high voltage and an output node of the HSHV driver; a biasing circuit configured to provide biasing voltages to the stack, the biasing circuit comprising a biasing stack of transistors of a first type; wherein; the output node is a drain node of an output transistor of the stack of transistors, adapted to be coupled to a reference voltage, the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage, and transistors of the stack and the biasing stack having desired operating voltages substantially smaller than the high voltage, transistors of the stack and the biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor, the last transistor of the stack is the output transistor and the first transistor of the stack is an input transistor of the HSHV driver, a gate node of the input transistor is configured to receive the input signal, the input signal being a level shifted signal, a source node of the input transistor is coupled to the high voltage; gate nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of the first to the last transistor of the biasing stack, common source-drain nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the biasing stack the biasing circuit further comprises a plurality of series connected resistors configured as a resistive voltage divider between the source node of the first transistor of the stack and the drain node of the last transistor of the stack, and resistive nodes of the resistive voltage divider connecting two consecutive resistors of the plurality of series connected resistors are coupled to the common source-drain nodes of the transistors of the stack in a one to one relationship. - View Dependent Claims (36)
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40-41. -41. (canceled)
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44. (canceled)
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53. A high speed high voltage (HSHV) driver comprising:
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a stack of transistors of a first type coupled between a reference voltage and an output node of the HSHV driver; a biasing circuit configured to provide biasing voltages to the stack, the biasing circuit comprising a biasing stack of transistors of a second type; wherein; the output node is a drain node of an output transistor of the stack of transistors adapted to be coupled to a high voltage, the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage, transistors of the stack and the biasing stack having desired operating voltages substantially smaller than the high voltage, transistors of the stack and the biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor, the last transistor of the stack is the output transistor and the first transistor of the stack is an input transistor of the HSHV driver, a gate node of the input transistor is configured to receive the input signal, a source node of the input transistor is coupled to the reference voltage; gate nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of the first to the last transistor of the biasing stack, common source-drain nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the biasing stack, the biasing circuit further comprises a plurality of series connected resistors configured as a resistive voltage divider between the source node of the first transistor of the stack and the drain node of the last transistor of the stack, and resistive nodes of the resistive voltage divider connecting two consecutive resistors of the plurality of series connected resistors are coupled to the gate nodes of the transistors of the stack. - View Dependent Claims (54)
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55. A high speed high voltage (HSHV) driver comprising:
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a stack of transistors of a first type coupled between a reference voltage and an output node of the HSHV driver; a biasing circuit configured to provide biasing voltages to the stack, the biasing circuit comprising a biasing stack of transistors of a second type; wherein; the output node is a drain node of an output transistor of the stack of transistors adapted to be coupled to a high voltage, the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage, transistors of the stack and the biasing stack having desired operating voltages substantially smaller than the high voltage, transistors of the stack and the biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor, the last transistor of the stack is the output transistor and the first transistor of the stack is an input transistor of the HSHV driver, a gate node of the input transistor is configured to receive the input signal, a source node of the input transistor is coupled to the reference voltage; gate nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of the first to the last transistor of the biasing stack, common source-drain nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the biasing stack, and the biasing circuit is configured to provide the biasing voltages of the HSHV driver at an output switching frequency of 0 Hz to 20 MHz. - View Dependent Claims (58)
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56. A high speed high voltage (HSHV) driver comprising:
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a stack of transistors of a first type coupled between a reference voltage and an output node of the HSHV driver; a biasing circuit configured to provide biasing voltages to the stack, the biasing circuit comprising a biasing stack of transistors of a second type; wherein; the output node is a drain node of an output transistor of the stack of transistors adapted to be coupled to a high voltage, the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage, transistors of the stack and the biasing stack having desired operating voltages substantially smaller than the high voltage, transistors of the stack and the biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor, the last transistor of the stack is the output transistor and the first transistor of the stack is an input transistor of the HSHV driver, a gate node of the input transistor is configured to receive the input signal, a source node of the input transistor is coupled to the reference voltage; gate nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of the first to the last transistor of the biasing stack, common source-drain nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the biasing stack, and the biasing circuit is configured to provide the biasing voltages of the HSHV driver at an output switching frequency of 0 Hz to 100 MHz. - View Dependent Claims (59)
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57. A high speed high voltage (HSHV) driver comprising:
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a stack of transistors of a first type coupled between a reference voltage and an output node of the HSHV driver; a biasing circuit configured to provide biasing voltages to the stack, the biasing circuit comprising a biasing stack of transistors of a second type; wherein; the output node is a drain node of an output transistor of the stack of transistors adapted to be coupled to a high voltage, the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage, transistors of the stack and the biasing stack having desired operating voltages substantially smaller than the high voltage, transistors of the stack and the biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor, the last transistor of the stack is the output transistor and the first transistor of the stack is an input transistor of the HSHV driver, a gate node of the input transistor is configured to receive the input signal, a source node of the input transistor is coupled to the reference voltage; gate nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of the first to the last transistor of the biasing stack, common source-drain nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the biasing stack, and the biasing circuit is configured to provide the biasing voltages of the HSHV driver at an output switching frequency above 100 MHz. - View Dependent Claims (60)
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61. A method for biasing a high speed high voltage HSHV driver, the method comprising:
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providing a first stack of transistors of a first type coupled between a high voltage and an output node of the HSHV driver; providing a second stack of transistors of a second type opposite the first type coupled between the output node and a reference voltage; providing biasing voltages to the first stack by way of a first biasing circuit coupled to the first stack, the first biasing circuit comprising a first biasing stack of transistors of the second type; and providing biasing voltages to the second stack by way of a second biasing circuit coupled to the second stack, the second biasing circuit comprising a second biasing stack of transistors of the first type, wherein; the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage, transistors of the first stack, the second stack, the first biasing stack and the second biasing stack having desired operating voltages substantially smaller than the high voltage, responsive to a change of state of the input signal, a transition phase of the first stack between an ON mode and an OFF mode comprises a sequential turning ON of a first transistor to a last transistor of the second stack responsive to the biasing voltages to the second stack, in synchrony with a sequential turning OFF of a first transistor to a last transistor of the first stack responsive to the biasing voltages to the first stack, the sequential turning ON of the first transistor to the last transistor of the second stack is in synchrony with a sequential turning ON of a first transistor to a last transistor of the second biasing stack, the sequential turning OFF of the first transistor to the last transistor of the first stack is in synchrony with a sequential turning OFF of a first transistor to a last transistor of the first biasing stack, and the providing of the biasing voltages to the first and the second stack comprises; responsive to a change of state of the input signal, controlling the biasing voltages by way of capacitive coupling during the transition phase of the first stack, and controlling the biasing voltages by way of resistive coupling after the transition phase. - View Dependent Claims (65, 66, 67, 68, 69)
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62-64. -64. (canceled)
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70. A method for biasing a stack of transistors of a first type for operation at a high voltage substantially higher than desired operating voltages of the transistors, the method comprising:
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coupling nodes of a biasing stack of transistors of a second type to nodes of the stack of transistors in a one to one relationship; based on the coupling, connecting gate nodes of the stack of transistors to source nodes of the biasing stack of transistors; based on the coupling, connecting gate nodes of the biasing stack of transistors to drain nodes of the stack of transistors; coupling a resistor network to the nodes of the stack of transistors; coupling a capacitor network to the nodes of the stack of transistors; during a transition phase of the stack of transistors, controlling biasing voltages to the stack of transistors by way of the coupled capacitor network; and after the transition phase, controlling the biasing voltages by way of the coupled resistor network, wherein; the transition phase is responsive to a change of state of an input signal to a first transistor of the stack of transistors, during the transition phase, transistors of the stack of transistors and the biasing stack of transistors sequentially change state, from an ON state to an OFF state, or vice versa, and the biasing voltage are controlled such as to not exceed desired operating voltages of the transistors of the stack of transistors during and after the transition phase.
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71. A high speed high voltage (HSHV) driver comprising:
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a stack of transistors of a second type coupled between a high voltage and an output node of the HSHV driver; a biasing circuit configured to provide biasing voltages to the stack, the biasing circuit comprising a biasing stack of transistors of a first type; wherein; the output node is a drain node of an output transistor of the stack of transistors, adapted to be coupled to a reference voltage, the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage, transistors of the stack and the biasing stack having desired operating voltages substantially smaller than the high voltage, transistors of the stack and the biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor, the last transistor of the stack is the output transistor and the first transistor of the stack is an input transistor of the HSHV driver, a gate node of the input transistor is configured to receive the input signal, the input signal being a level shifted signal, a source node of the input transistor is coupled to the high voltage; gate nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of the first to the last transistor of the biasing stack, common source-drain nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the biasing stack, the biasing circuit further comprises a plurality of series connected resistors configured as a resistive voltage divider between the source node of the first transistor of the stack and the drain node of the last transistor of the stack, and resistive nodes of the resistive voltage divider connecting two consecutive resistors of the plurality of series connected resistors are coupled to the gate nodes of the transistors of the stack. - View Dependent Claims (72)
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73. A high speed high voltage (HSHV) driver comprising:
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a stack of transistors of a second type coupled between a high voltage and an output node of the HSHV driver; a biasing circuit configured to provide biasing voltages to the stack, the biasing circuit comprising a biasing stack of transistors of a first type; wherein; the output node is a drain node of an output transistor of the stack of transistors, adapted to be coupled to a reference voltage, the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage, transistors of the stack and the biasing stack having desired operating voltages substantially smaller than the high voltage, transistors of the stack and the biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor, the last transistor of the stack is the output transistor and the first transistor of the stack is an input transistor of the HSHV driver, a gate node of the input transistor is configured to receive the input signal, the input signal being a level shifted signal, a source node of the input transistor is coupled to the high voltage; gate nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of the first to the last transistor of the biasing stack, common source-drain nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the biasing stack, and the biasing circuit is configured to provide the biasing voltages of the HSHV driver at an output switching frequency of 0 Hz to 20 MHz. - View Dependent Claims (76)
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74. A high speed high voltage (HSHV) driver comprising:
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a stack of transistors of a second type coupled between a high voltage and an output node of the HSHV driver; a biasing circuit configured to provide biasing voltages to the stack, the biasing circuit comprising a biasing stack of transistors of a first type; wherein; the output node is a drain node of an output transistor of the stack of transistors, adapted to be coupled to a reference voltage, the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage, transistors of the stack and the biasing stack having desired operating voltages substantially smaller than the high voltage, transistors of the stack and the biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor, the last transistor of the stack is the output transistor and the first transistor of the stack is an input transistor of the HSHV driver, a gate node of the input transistor is configured to receive the input signal, the input signal being a level shifted signal, a source node of the input transistor is coupled to the high voltage; gate nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of the first to the last transistor of the biasing stack, common source-drain nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the biasing stack, and the biasing circuit is configured to provide the biasing voltages of the HSHV driver at an output switching frequency of 0 Hz to 100 MHz. - View Dependent Claims (77)
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75. A high speed high voltage (HSHV) driver comprising:
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a stack of transistors of a second type coupled between a high voltage and an output node of the HSHV driver; a biasing circuit configured to provide biasing voltages to the stack, the biasing circuit comprising a biasing stack of transistors of a first type; wherein; the output node is a drain node of an output transistor of the stack of transistors, adapted to be coupled to a reference voltage, the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage, transistors of the stack and the biasing stack having desired operating voltages substantially smaller than the high voltage, transistors of the stack and the biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor, the last transistor of the stack is the output transistor and the first transistor of the stack is an input transistor of the HSHV driver, a gate node of the input transistor is configured to receive the input signal, the input signal being a level shifted signal, a source node of the input transistor is coupled to the high voltage; gate nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of the first to the last transistor of the biasing stack, common source-drain nodes of the first to the last transistor of the stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the biasing stack, and the biasing circuit is configured to provide the biasing voltages of the HSHV driver at an output switching frequency above 100 MHz. - View Dependent Claims (78)
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Specification