DIE STACK TEST ARCHITECTURE AND METHOD

• US 20170269145A1
• Filed: 06/07/2017
• Published: 09/21/2017
• Est. Priority Date: 02/21/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Granted Patent: US 10,067,188 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/2607 Circuits therefor G01R31/2642 takes precedence
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552
• CPC Class Codes: H01J 2237/15 Means for deflecting or directing discharge
• CPC Class Codes: H01J 2237/30472 Controlling the beam
• CPC Class Codes: H01J 37/3007 Electron or ion-optical systems electron or ion-optical details H01J37/06 - H01J37/153
• CPC Class Codes: H01J 37/3171 for ion implantation plasma immersion ion implantation H01J37/32412

Abstract

A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

Claims

1. An integrated circuit die comprising:

(a) a first surface having parallel test input contacts, a test data input contact, test control input contacts, a test data output contact, and parallel test input and output contacts;

(b) a second surface opposite the first surface, the second surface having parallel test output contacts, a test data output contact, test control output contacts, a test data input contact, and parallel test input and output contacts;

(c) a test control port having leads coupled to the first surface test data input, the first surface test control input, the first surface test data output contacts, the second surface test data output, the second surface test control output, and the second surface test data input contacts, and having control outputs;

(d) parallel scan circuitry including;

(i) decompressor circuitry having parallel inputs coupled to the first surface parallel test input contacts and parallel test data outputs;

(ii) parallel scan paths, each parallel scan path having a test data input connected to a test data output of the decompressor circuitry, a control input coupled to a control output of the test control port, and parallel test data outputs; and

(iii) compactor circuitry having parallel inputs connected to the parallel test data outputs of the parallel scan paths and parallel compacted data outputs;

(e) first coupling circuitry having inputs coupled to the parallel compacted data outputs of the parallel scan circuitry, a control input coupled to a control output of the test control port, and outputs coupled to the parallel test output contacts of the second surface; and

(f) second coupling circuitry having inputs coupled to the parallel test input contacts of the first surface, a control input coupled to a control output of the test control port, and outputs coupled to the parallel test output contacts of the second surface.

2. The integrated circuit die of claim 1 in which the first coupling circuitry includes tri-state buffers and the second coupling circuitry includes tri-state buffers.

3. The integrated circuit of claim 1 in which the test control port includes an instruction register coupled to the first surface test data input contact, the first surface test control input contacts, and the first surface test data output contacts, and having at least one of the control outputs.

4. The integrated circuit of claim 1 in which the test control port includes a data register coupled to the first surface test data input contact, the first surface test control input contacts, and the first surface test data output contacts.

5. The integrated circuit of claim 1 in which the test control port includes an instruction register coupled to the first surface test data input contact, the first surface test control input contacts, and the first surface test data output contacts, and having at least one of the control outputs, and includes a data register coupled to the first surface test data input contact, the first surface test control input contacts, and the first surface test data output contacts.