DISPLAY PANEL AND DRIVING METHOD THEREOF, AND DISPLAY APPARATUS

• US 20170269416A1
• Filed: 10/10/2016
• Published: 09/21/2017
• Est. Priority Date: 10/28/2015
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: MIAO, Jinghua, CHEN, Chungchun, DONG, Xue, CHEN, Xiaochuan, XU, Rui, LI, Mubing, YANG, Ming
• Granted Patent: US 10,453,377 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2310/0278 Details of driving circuits arranged to drive both scan and data electrodes
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 3/2003 Display of colours specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 3/2085 Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

A display panel is provided which includes a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction substantially perpendicular to the first direction, and a driving circuit. The driving circuit is arranged at an end of the data lines for supplying a scan signal to the gate lines and supplying grayscale signals to the data lines.

Claims

1. (canceled)

2. A display panel comprising:

a plurality of pixel units arranged in an array, each of the pixel units having a respective pixel thin-film transistor;

a plurality of gate lines extending in a first direction, each of the gate lines connected to a respective row of pixel units in the array;

a plurality of data lines extending in a second direction substantially perpendicular to the first direction, each of the data lines connected to a respective column of pixel units in the array;

a driving circuit arranged at an end of the data lines and comprising;

a plurality of common terminals for outputting a scan signal and respective grayscale signals;

a switch network operable to selectively couple the common terminals to the gate lines or the data lines; and

a driving unit configured to a) supply the scan signal sequentially to the plurality of common terminals in a plurality of first time periods that are temporally separate and cause, in each first time period in which the scan signal is supplied to one of the common terminals, the switch network to couple the plurality of common terminals to the plurality of gate lines respectively such that the scan signal is applied to one of the gate lines, and to b) supply, in each of second time periods immediately subsequent to respective first time periods, the grayscale signals to the plurality of common terminals and cause the switch network to couple each of the common terminals to a respective one of the data lines such that the grayscale signals are transferred to the array of pixel units; and

a plurality of gate voltage storage capacitors each connected between a respective one of the gate lines and a predetermined voltage and operable to enable, after being charged by the scan signal applied to the respective gate line, the pixel thin-film transistors of a row of pixel units connected to the gate line to remain turned-on in the second time period in which the grayscale signals for the row of pixel units are supplied.

3. The display panel of claim 2, wherein the driving unit is further configured to supply a reversal signal sequentially to the plurality of common terminals in a plurality of third time periods immediately subsequent to respective second time periods and cause, in each third time period in which the reversal signal is supplied to one of the common terminals, the switch network to couple the plurality of common terminals to the plurality of gate lines respectively to discharge the charged gate voltage storage capacitor, the reversal signal having an opposite polarity to that of the scan signal.

4. The display panel of claim 3, wherein the switch network comprises:

a plurality of first switches operable to couple the plurality of common terminals to the plurality of gate lines respectively in response to a first gate control signal supplied by the driving unit, the first gate control signal being synchronous with one of the scan signal and the reversal signal; and

a plurality of second switches operable to couple the plurality of common terminals to the plurality of gate lines respectively in response to a second gate control signal supplied by the driving unit, the second gate control signal being synchronous with the other one of the scan signal and the reversal signal.

5. The display panel of claim 4, wherein the first switch and the second switch that are connected to the same gate line share the same common terminal.

6. The display panel of claim 4, wherein each of the first switches comprises a transistor having a gate for receiving the first gate control signal, a first electrode connected to a respective one of the common terminals, and a second electrode connected to a respective one of the gate lines.

7. The display panel of claim 4, wherein each of the second switches comprises a transistor having a gate for receiving the second gate control signal, a first electrode connected to a respective one of the common terminals, and a second electrode connected to a respective one of gate lines.

8. The display panel of claim 2, wherein the driving unit is further configured to in each of the second time periods:

supply, in a first time interval, grayscale signals for odd pixel units in a respective row of pixel units to the plurality of common terminals and cause the switch network to couple the plurality of common terminals to odd ones of the data lines respectively; and

supply, in a second time interval, grayscale signals for even pixel units in the respective row of pixel units to the plurality of common terminals and cause the switch network to couple the plurality of common terminals to even ones of the data lines respectively.

9. The display panel of claim 8, wherein the switch network further comprises:

a plurality of third switches operable to couple the plurality of common terminals to the odd ones of the data lines in the first time interval in response to a first data control signal supplied by the driving unit; and

a plurality of fourth switches operable to couple the plurality of common terminals to the even ones of the data lines in the second time interval in response to a second data control signal supplied by the driving unit.

10. The display panel of claim 9, wherein the driving unit is further configured such that the first data control signal and the second data control signal are successively supplied.

11. The display panel of claim 9, wherein each of the third switches is paired to a respective one of the fourth switches, wherein in each pair the third switch and the fourth switch share the same common terminal, and wherein the odd data line connected to the third switch is adjacent to the even data line connected to the fourth switch.

12. The display panel of claim 9, wherein each of the third switches comprises a transistor having a gate for receiving the first data control signal, a first electrode connected to a respective one of the common terminals, and a second electrode connected to a respective one of the odd data lines.

13. The display panel of claim 9, wherein each of the fourth switches comprises a transistor having a gate for receiving the second data control signal, a first electrode connected to a respective one of the common terminals, and a second electrode connected to a respective one of the even data lines.

14. A display apparatus comprising:

a timing controller configured to generate output image data based on input image data; and

the display panel as recited in claim 2, the display panel configured to display an image based on the output image data.

15. The display apparatus of claim 14, wherein the driving unit is further configured to supply a reversal signal sequentially to the plurality of common terminals in a plurality of third time periods immediately subsequent to respective second time periods and cause, in each third time period in which the reversal signal is supplied to one of the common terminals, the switch network to couple the plurality of common terminals to the plurality of gate lines respectively to discharge the charged gate voltage storage capacitor, the reversal signal having an opposite polarity to that of the scan signal;

wherein the timing controller is further configured to generate a first data corresponding to the scan signal and a second data corresponding to the reversal signal; and

wherein the driving unit is further configured to generate the scan signal, the reversal signal and the grayscale signals based on the first data, the second data and the output image data respectively.

16. A method of driving the display panel as recited in claim 2, comprising:

for each row of pixel units in the array;

supplying the scan signal to the gate line connected to the row of pixel units in a first time period; and

supplying respective grayscale signals to the plurality of data lines in a second time period immediately subsequent to the first time period.

17. The method of claim 16, wherein supplying the scan signal to the gate line connected to the row of pixel units comprises charging the gate voltage storage capacitor connected to the gate line with the scan signal, the charged gate voltage storage capacitor enabling the pixel thin-film transistors of the row of pixel units to remain turned-on during the second time period.

18. The method of claim 17, wherein supplying respective grayscale signals to the plurality of data lines comprises:

supplying grayscale signals for odd pixel units in the row of pixel units to odd ones of the data lines in a first time interval; and

supplying grayscale signals for even pixel units in the row of pixel units to even ones of the data lines in a second time interval.

19. The method of claim 16, further comprising supplying a reversal signal sequentially to the gate line connected to the row of pixel units in a third time period immediately subsequent to the second time period, the reversal signal having an opposite polarity to that of the scan signal.

20. The method of claim 19, further comprising generating, prior to supplying the scan signal, a first data corresponding to the scan signal and a second data corresponding to the reversal signal to enable the driving unit to generate the scan signal and the reversal signal based on the first data and the second data respectively.