AUTONOMOUS DRAM SCRUB AND ERROR COUNTING

• US 20170269979A1
• Filed: 03/15/2016
• Published: 09/21/2017
• Est. Priority Date: 03/15/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gollub, Marc A., Maule, Warren E., Sawan, Tony E., Chinnakkonda Vidyapoornachary, Diyanesh B.
• Granted Patent: US 10,628,248 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing

Abstract

An aspect includes a method for dynamic random access memory (DRAM) scrub and error counting. A scrub operation is performed at memory locations in a DRAM. The performing includes, for each of the memory locations: receiving a refresh command at the DRAM; executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and incrementing an error count in response to detecting an error during the executing. The method also includes comparing the error count to an error threshold. An alert is initiated in response to the error count exceeding the error threshold.

Claims

1. A method of dynamic random access memory (DRAM) scrub and error counting in a memory of a computer system, the method comprising:

performing a scrub operation at memory locations in a DRAM, the performing including, for each of the memory locations;

receiving a refresh command at the DRAM;

executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and

incrementing an error count in response to detecting an error during the executing;

comparing the error count to an error threshold; and

initiating an alert in response to the error count exceeding the error threshold.

2. The method of claim 1, wherein the scrub operation is performed for all memory locations in the DRAM.

3. The method of claim 1, wherein the performing is independent of a memory controller.

4. The method of claim 1, wherein the error threshold indicates a number of errors in excess of an expected number of errors.

5. The method of claim 1, wherein the comparing and the initiating are in response to a request from a memory controller.

6. The method of claim 1, wherein a refresh is performed in response to the refresh command at a second memory location that is different than the memory location.

7. The method of claim 1, wherein the refresh command is received from a memory controller.

8. The method of claim 1, wherein the DRAM is in a self-refresh mode and the refresh command is received from the DRAM.

9. The method of claim 1, further comprising:

resetting the error count to zero subsequent to the comparing; and

repeating the performing and comparing.

10. The method of claim 1, wherein the alert is sent to a memory controller via a dedicated pin on the DRAM.

11. A memory system comprising:

a memory device, the memory device including a dynamic random access memory (DRAM) and configured to;

perform a scrub operation at memory locations in the DRAM, the performing including, for each of the memory locations;

receiving a refresh command at the DRAM;

executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and

incrementing an error count in response to detecting an error during the executing;

compare the error count to an error threshold; and

initiate an alert in response to the error count exceeding the error threshold.

12. The memory system of claim 11, wherein the scrub operation is performed for all memory locations in the DRAM.

13. The memory system of claim 11, wherein the performing is independent of a memory controller.

14. The memory system of claim 11, wherein the error threshold indicates a number of errors in excess of an expected number of errors.

15. The memory system of claim 11, wherein a refresh is performed in response to the refresh command at a second memory location that is different than the memory location.

16. The memory system of claim 11, wherein the refresh command is received from a memory controller.

17. The memory system of claim 11, wherein the DRAM is in a self-refresh mode and the refresh command is received from the DRAM.

18. A computer program product for dynamic random access memory (DRAM) scrub and error counting in a memory of a computer system, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by processing circuitry to cause the processing circuitry to:

perform a scrub operation at memory locations in the DRAM, the performing including, for each of the memory locations;

receiving a refresh command at the DRAM;

executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and

incrementing an error count in response to detecting an error during the executing;

compare the error count to an error threshold; and

initiate an alert in response to the error count exceeding the error threshold.

19. The computer program product of claim 18, wherein the performing is independent of a memory controller.

20. The computer program product of claim 18, wherein the error threshold indicates a number of errors in excess of an expected number of errors.