SHIFT REGISTER, GOA CIRCUIT CONTAINING THE SAME, AND RELATED DISPLAY DEVICE

• US 20170270879A1
• Filed: 07/01/2016
• Published: 09/21/2017
• Est. Priority Date: 10/28/2015
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: HAN, Mingfu, HAN, Seungwoo, SHANG, Guangliang, CHOI, Hyunsic, YAO, Xing, ZHENG, Haoliang, DONG, Xue, JUN, Jungmok, IM, Yunsik
• Granted Patent: US 10,192,504 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

The present disclosure provides a shift register, including: an input unit, an output control unit, a first pull-down unit, a second pull-down unit, a reset unit, and a pull-down control unit. The input unit comprises a control terminal connected to a signal input terminal, a first terminal connected to a first voltage terminal, and a second terminal connected to a first node. The output control unit comprises a control terminal connected to the first node, a first terminal connected to a first clock signal terminal, and a second terminal connected to a signal output terminal. The first pull-down unit comprises a control terminal connected to a second node, a first terminal connected to the first node, and a second terminal connected to a compensation signal terminal. The second pull-down unit comprises a control terminal connected to the compensation signal terminal, and a first terminal connected to the second node.

Claims

1-21. -21. (canceled)

22. A shift register, comprising:

an input unit, an output control unit, a first pull-down unit, a second pull-down unit, a reset unit, and a pull-down control unit, wherein;

the input unit comprises a control terminal connected to a signal input terminal, a first terminal connected to a first voltage terminal, and a second terminal connected to a first node;

the output control unit comprises a control terminal connected to the first node, a first terminal connected to a first clock signal terminal, and a second terminal connected to a signal output terminal;

the first pull-down unit comprises a control terminal connected to a second node, a first terminal connected to the first node, and a second terminal connected to a compensation signal terminal;

the second pull-down unit comprises a control terminal connected to the compensation signal terminal, a first terminal connected to the second node, and a second terminal connected to a second voltage terminal;

the pull-down control unit comprises a first control terminal connected to the signal input terminal, a second control terminal connected to the first node, a first terminal connected to the second node, a second terminal connected to the second voltage terminal;

the reset unit comprises a control terminal connected to a reset signal terminal, a first terminal connected to the first node, a second terminal connected to the second voltage terminal;

the first clock signal terminal and the second clock signal terminal input signals of opposite polarities in a scanning period in a frame, and input a turn-off signal in a blanking period in a frame; and

the compensation signal terminal inputs a turn-off signal in the scanning period in a frame and inputs a turn-on signal in the blanking period in a frame.

23. The shift register according to claim 22, the second pull-down unit comprising a first thin-film transistor (TFT), wherein the first TFT comprises:

a gate electrode connected to the compensation signal terminal, a source electrode connected to a second voltage terminal, a drain electrode connected to the second node.

24. The shift register according to claim 22, the first pull-down unit comprising a fourth TFT, wherein the fourth TFT comprises:

a gate electrode connected to the second node, a source electrode connected to the first node, and a drain electrode connected to the compensation signal terminal.

25. The shift register according to claim 22, the output control unit comprising a thirteenth TFT and a capacitor, wherein the thirteenth TFT comprises:

a gate electrode connected to the first node, a source electrode connected to the first clock signal terminal, and a drain electrode connected to the signal output terminal, the capacitor being connected between the first node and the signal output terminal.

26. The shift register according to claim 22, further comprising a third pull-down unit, wherein the third pull-down unit comprises:

a first control terminal connected to the second clock signal terminal, a first terminal connected to the signal output terminal, and a second terminal connected to the second voltage terminal.

27. The shift register according to claim 26, the third pull-down unit comprising a second TFT, wherein the second TFT comprises:

a gate electrode connected to the second clock signal terminal, a source electrode connected to the signal output terminal, a drain electrode connected to the compensation signal terminal.

28. The shift register according to claim 27, wherein the third pull-down unit further comprises a second control terminal connected to the second node, a turn-on signal inputted by the second control terminal connecting the compensation signal terminal with the signal output terminal.

29. The shift register according to claim 28, the first pull-down unit further comprising a third TFT, wherein the third TFT comprises:

a gate electrode connected to the second node, a source electrode connected to the signal output terminal, and a drain electrode connected to the compensation signal terminal.

30. The shift register according to claim 22, the pull-down control unit comprising a sixth TFT and an eighth TFT, wherein:

the sixth TFT comprises;

a gate electrode connected to the first node, a source electrode connected to the second node, and a drain electrode connected to the second voltage terminal; and

the eighth TFT comprises;

a gate electrode and a drain electrode connected to the second clock signal terminal, and a source electrode connected to the second node.

31. The shift register according to claim 30, the pull-down control unit further comprising a third control terminal connected to the first clock signal terminal and a fourth control terminal connected to the signal input terminal.

32. The shift register according to claim 31, further comprising a fifth TFT connected between the second voltage terminal and the second node, wherein the fifth TFT comprises:

a gate electrode connected to the signal input terminal, a drain electrode connected to the second clock signal terminal, and a source electrode connected to the second node.

33. The shift register according to claim 31, further comprising a seventh TFT connected between the compensation signal terminal and the second node, wherein the seventh TFT comprises:

a gate electrode connected the first clock signal terminal, a drain electrode connected to the compensation signal terminal, and a source electrode connected to the second node.

34. The shift register according to claim 22, the reset unit comprising a tenth TFT, wherein the tenth TFT comprises:

a gate electrode connected to the reset signal terminal;

a drain electrode connected to the second voltage terminal; and

a source electrode connected to the first node.

35. The shift register according to claim 34, the reset unit further comprising a ninth TFT connected between the output signal terminal and the second voltage terminal, wherein the ninth TFT comprises:

a gate electrode connected to the reset signal terminal;

a drain electrode connected to the second voltage terminal; and

a source electrode connected to the output signal terminal.

36. The shift register according to claim 22, further comprising a final-reset unit, the final-reset unit comprising a control terminal connected to a total reset signal terminal, an input terminal connected to the first node, and a second terminal connected to the second voltage terminal, wherein:

the final-reset unit connects the first node with the second voltage terminal when the total reset terminal inputs a turn-on signal to the final-reset unit.

37. The shift register according to claim 36, the final-reset unit comprising an eleventh TFT, wherein the eleventh TFT comprises a gate electrode connected to the total reset signal terminal, a source electrode connected to the first node, and a drain electrode connected to the second voltage terminal.

38. The shift register according to claim 22, further comprising a start-reset unit, wherein the start-reset unit comprises a control terminal and an input terminal connected to a frame-start signal terminal, and a second terminal connected to the second node, wherein:

the start-reset unit pulls up the voltage level of the second node when the frame-start signal terminal inputs a turn-on signal to the start-reset unit.

39. The shift register according to claim 38, the start-reset unit comprising a twelfth TFT, wherein the twelfth TFT comprises a gate electrode and a source electrode connected to the frame-start signal terminal, and a drain electrode connected to the second node.

40. A gate-driver on array (GOA) circuit, comprising a plurality of cascading shift register according to claim 22, wherein:

except for a last shift register, the signal output terminal of one other shift register inputs a triggering signal to the signal input terminal of a next and adjacent shift register.

42. A display device, comprising one or more of the GOA circuits according to claim 40.

41. The GOA circuit according to claim 41, wherein:

except for a first shift register, the signal output terminal of one other shift register inputs a reset signal to the reset signal terminal of a previous and adjacent shift register.