METHOD AND SYSTEM FOR USING DOWNGRADED FLASH DIE FOR CACHE APPLICATIONS

• US 20170271030A1
• Filed: 03/18/2016
• Published: 09/21/2017
• Est. Priority Date: 03/18/2016
• Status: Abandoned Application

• Current Assignee: Alibaba Group Holding Ltd.
• Original Assignee: Alibaba Group Holding Ltd.
• Inventors: LI, Shu
• Application Number:
  US15/074,961
• Publication Number:
  US 20170271030A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/281 Single cache
• CPC Class Codes: G06F 2212/313 In storage device
• CPC Class Codes: G06F 2212/466 Metadata, control data
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A method and apparatus for using low-cost un-qualified dies suitable for an SSD cache application in an SSD cache are disclosed. Embodiments of the present invention enable production of a cache-die SSD with sufficient data retention and endurance to meet demands of modern data centers while reducing infrastructure costs. According to one embodiment, a method of identifying and using low-cost un-qualified dies suitable for an SSD cache application in an SSD cache is disclosed. The method includes extracting application data from the SSD cache application, modeling a behavior of the SSD cache application based on the application data, characterizing a first un-qualified die to determine at least one quantified property of the first un-qualified die, and testing the at least one quantified property of the first un-qualified die against the modeled behavior of the SSD cache application to determine if the un-qualified die is suitable for the SSD cache.

Claims

1. A method of identifying and using un-qualified dies suitable for an SSD cache application in an SSD cache, the method comprising:

extracting application data from the SSD cache application;

modeling a behavior of the SSD cache application based on the application data to produce a modeled behavior;

characterizing a first un-qualified die to determine at least one quantified property of the first un-qualified die; and

testing the at least one quantified property of the first un-qualified die against the modeled behavior of the SSD cache application to determine if the un-qualified die is suitable for use in the SSD cache.

2. The method of claim 1, further comprising repeating the extracting, the modeling, the characterizing, and the testing until a sufficient number of un-qualified dies are identified to construct an SSD cache meeting prescribed requirements of the SSD cache application.

3. The method of claim 2, further comprising enclosing the sufficient number of un-qualified dies in packaging to form an integrated circuit.

4. The method of claim 3, further comprising constructing a cache-die SSD using the integrated circuit, wherein the cache-die SSD meets a requirement of the modeled behavior of the SSD cache application.

5. The method of claim 3, further comprising:

constructing a cache-die SSD using the integrated circuit;

testing the cache-die SSD against a requirement of the modeled behavior of the SSD cache application; and

generating a specification of the cache-die SSD.

6. The method of claim 5, further comprising tuning the SSD cache application for compatibility with the cache-die SSD.

7. The method of claim 6, further comprising using corresponding device management firmware and software to control and monitor the cache-die SSD for the SSD cache application based on the modeled behavior.

8. The method of claim 3, wherein the un-qualified die comprises a NAND Flash die.

9. The method of claim 3, wherein the un-qualified die is characterized as having an increased noise margin to reduce an error rate of the un-qualified die.

10. The method of claim 3, wherein the un-qualified die is characterized in that a programmed voltage value of the un-qualified die is increased when a charge is placed on a floating gate thereof to mitigate write latency.

11. A solid state drive comprising:

a plurality of un-qualified dies for storing data; and

an SSD controller, comprising;

a first interface for sending data to and receiving data from the plurality of un-qualified dies;

a second interface for sending data to and receiving data from a CPU;

a first plurality of modules coupled to the first and second interfaces, the first plurality of modules for compressing, for encrypting, and for ECC encoding data for storage using the plurality of un-qualified dies; and

a second plurality of modules coupled to the first and second interfaces, the second plurality of modules for ECC decoding, for decrypting, and for decompressing data retrieved from the plurality of un-qualified dies.

12. The solid state drive of claim 11, wherein the plurality of un-qualified dies comprises NAND Flash and the first interface is a NAND Flash interface.

13. The solid state drive of claim 11, wherein the ECC encoding comprises adjustable, on-the fly ECC encoding based on an observed error rate of the plurality of un-qualified dies.

14. The solid state drive of claim 13, wherein the adjustable, on-the fly ECC encoding is configured to use a greater number of redundancy bits when the observed error rate exceeds a threshold.

15. The solid state drive of claim 13, wherein the adjustable, on-the fly ECC encoding is configured to encode fewer bits when the observed error rate exceeds a threshold.

16. The solid state drive of claim 11, wherein the plurality of un-qualified dies comprises an increased noise margin to reduce an error rate thereof.

17. The solid state drive of claim 11, wherein the plurality of un-qualified dies is characterized in that a programmed voltage value of the plurality of un-qualified dies is increased when a charge is placed on a floating gate thereof to mitigate write latency.

18. A cache-die SSD architecture comprising:

a PIPE interface configured to communicate with a CPU;

a NAND interface communicatively coupled to a plurality of un-qualified NAND cache dies; and

an adjustable ECC encoding module coupled to the PIPE interface and the NAND interface, wherein the adjustable ECC encoding module automatically adjusts an encoding rate thereof based on an observed error rate of the plurality of un-qualified NAND cache dies and uses an increased number of redundancy bits when the observed error rate reaches a predetermined threshold.

19. The cache-die SSD architecture of claim 18, further comprising an encryption module communicatively coupled to the PIPE interface and the ECC encoding module, wherein data received by the PIPE interface is encrypted by the encryption module before being sent to the ECC encoding module.

20. The cache-die SSD architecture of claim 19, further comprising a compression module communicatively coupled to the PIPE interface and the encryption module, wherein data received by the PIPE interface is compressed by the compression module before being sent to the encryption module.