SEMICONDCUTOR PACKAGE AND MANUFACTURING PROCESS THEREOF

• US 20170271248A1
• Filed: 05/06/2016
• Published: 09/21/2017
• Est. Priority Date: 03/21/2016
• Status: Active Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Yu-Feng, Chen, Chih-Hua, Yu, Chen-Hua, Liu, Chung-Shi, Kuo, Hung-Jui, Tsai, Hui-Jung, Tsai, Hao-Yi
• Granted Patent: US 10,276,402 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.

Claims

1. A semiconductor package comprising:

a first redistribution layer;

a first die, encapsulated within a molding material and coupled to the first redistribution layer;

a second redistribution layer, disposed on the molding material on the first die and coupled to the first die, wherein the second redistribution layer comprises a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion; and

a surface coating layer, covering a portion of the topmost metallization layer and exposing the concave portion of the at least one contact pad.

2. The semiconductor package as claimed in claim 1, further comprising a second die, disposed on and electrically connected to the second redistribution layer.

3. The semiconductor package as claimed in claim 2, further comprising at least one conductive element, disposed on the concave portion of the at least one contact pad.

4. The semiconductor package as claimed in claim 3, wherein a plane parallel to a surface of the second die is above a topmost point of the at least one conductive element.

5. The semiconductor package as claimed in claim 1, further comprising at least one through via penetrating through the molding material, and electrically connecting the first redistribution layer and the second redistribution layer.

6. The semiconductor package as claimed in claim 1, wherein the concave portion of the at least one contact pad exposes a sidewall of the surface coating layer, and a distance measuring from a lowest point of the concave portion of the at least one contact pad to a top surface of the second redistribution layer in a normal direction of the surface of the second redistribution layer is greater than a height of an exposed sidewall of the surface coating layer in the normal direction.

7. The semiconductor package as claimed in claim 1, wherein the first die is a sensor chip.

8. A semiconductor package comprising:

a first die molded in a molding material;

an interconnect structure, disposed aside of the molding material, wherein the interconnect structure comprises;

a plurality of through vias, penetrating through the molding material;

a first redistribution layer, disposed at a first side of the first die and connected to the through vias;

a second redistribution layer, disposed at a second side of the first die, on the molding material and above the first redistribution layer, and connected to the through vias, wherein the first redistribution layer and the second redistribution layer are connected by the through vias and the second redistribution layer comprises;

a topmost metallization layer having at least one contact pad and a surface coating layer, and the surface coating layer covers a portion of the topmost metallization layer, and the at least one contact pad includes a concave portion exposed by the surface coating layer; and

at least one conductive element, disposed on the concave portion of the at least one contact pad.

9. The semiconductor package as claimed in claim 8, further comprising a second die disposed on and electrically connected to the topmost metallization layer of the second redistribution layer.

10. The semiconductor package as claimed in claim 9, wherein a plane parallel to a surface of the second die is above a topmost point of the at least one conductive element.

11. The semiconductor package as claimed in claim 8, wherein the first die includes at least one fingerprint sensor.

12. The semiconductor package as claimed in claim 8, wherein the concave portion of the at least one contact pad exposes a portion of a sidewall of the surface coating layer, and a distance measuring from a lowest point of the concave portion of the at least one contact pad to a top surface of the second redistribution layer in a normal direction of the surface of the second redistribution layer is greater than a height of the exposed portion of the sidewall of the surface coating layer in the normal direction.

13. The semiconductor package as claimed in claim 8, wherein the surface coating layer comprises titanium and copper.

14. A manufacturing process for a semiconductor package, comprising:

providing a carrier;

forming a first redistribution layer on the carrier, wherein the first redistribution layer comprises a metallization layer having at least one contact pad on the carrier;

forming a plurality of through vias on the first redistribution layer, wherein the through vias are electrically connected to the first redistribution layer;

disposing a first die on the first redistribution layer;

encapsulating the first die and the through vias in a molding material;

forming a second redistribution layer on the molding material and on a front surface of the first die, wherein the second redistribution layer is electrically connected to the through vias and the first die;

disposing a protection layer on the second redistribution layer;

debonding the carrier from the first redistribution layer to expose the metallization layer; and

etching the metallization layer of the first redistribution layer to form a concave portion in the at least one contact pad.

15. The process as claimed in claim 14, further comprising:

disposing at least one conductive element on the at least one contact pad, wherein the second die and the at least one conductive element are electrically connected to the first redistribution layer; and

disposing a second die on the first redistribution layer.

16. The process as claimed in claim 14, wherein forming the first redistribution layer on the carrier comprises:

forming a polymer dielectric material layer on the carrier;

patterning the polymer dielectric material layer to form openings penetrating through the polymer dielectric material layer;

forming a surface coating layer over the polymer dielectric material layer and conformally covering the openings;

forming the metallization layer on the polymer dielectric material layer to fill the openings; and

patterning the metallization layer and the surface coating layer.

17. The process as claimed in claim 14, wherein prior to forming the second redistribution layer, the process further comprises:

planarizing the molding material and the through vias to expose the front surface of the first die.

18. The process as claimed in claim 16, wherein etching the metallization layer of the first redistribution layer to form a concave portion in the at least one contact pad comprises:

dry etching the surface coating layer covering the at least one contact pad of the metallization layer of the first redistribution layer to remove a portion of the surface coating layer; and

wet etching the surface coating layer and the at least one contact pad to form the concave portion in the at least one contact pad.

19. The process as claimed in claim 18, wherein the surface coating layer comprises titanium and copper, dry etching the surface coating layer comprises performing a titanium dry etching process and wet etching the at least one contact pad comprises performing a titanium wet etching process.

20. The process as claimed in claim 18, wherein the concave portion of the at least one contact pad exposes a portion of a sidewall of the surface coating layer, and a distance from a lowest point of the concave portion of the at least one contact pad to a front surface of the first redistribution layer in a normal direction of the front surface of the first redistribution layer is greater than a height of the exposed portion of the sidewall of the surface coating layer in the normal direction.