Semiconductor Devices for Integration with Light Emitting Chips and Modules Thereof

• US 20170271313A1
• Filed: 06/06/2017
• Published: 09/21/2017
• Est. Priority Date: 11/18/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Bonart, Dietrich, Weidgans, Bernhard, Gatterbauer, Johann, Gross, Thomas, Heigl, Martina
• Granted Patent: US 9,966,368 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/14692 Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2933/0058 relating to optical field-shaping elements
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 31/055 where light is absorbed and re-emitted at a different wavelength by the optical element directly associated or integrated with the PV cell, e.g. by using luminescent material, fluorescent concentrators or up-conversion arrangements
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/405 : Reflective materials
• CPC Class Codes: H01L 33/44 : characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/46 : Reflective coating, e.g. dielectric Bragg reflector
• CPC Class Codes: H01L 33/60 : Reflective elements
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H10K 50/856 : comprising reflective means
• CPC Class Codes: Y02E 10/52 : PV systems with concentrators

Abstract

A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad.

Claims

1. A semiconductor device comprising:

an active region disposed in a semiconductor substrate;

an uppermost metal level comprising metal lines, the uppermost metal level disposed over the semiconductor substrate;

contact pads disposed at a major surface of the semiconductor device, the contact pads coupled to the metal lines in the uppermost metal level;

an isolation region separating the contact pads disposed at the major surface, wherein adjacent contact pads are electrically isolated from one another by a portion of the isolation region; and

reflective structures disposed between the upper metal level and the contact pads, wherein each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pads.

2. The device of claim 1, further comprising:

a contact via coupled between the one of the metal lines in the uppermost metal level to one of the contact pads; and

a sidewall spacer electrically isolating the contact via from the reflective structures.

3. The device of claim 1, wherein the reflective structures comprise a different composition from the contact pads and the metal lines in the uppermost metal level.

4. The device of claim 1, wherein the contact pads and the reflective structures together are configured to reflect all light in visible wavelength above 400 nm falling on the major surface of the semiconductor device.

5. The device of claim 1, further comprising a light emitting diode (LED) chip directly soldered to the contact pads.

6. The device of claim 1, wherein the reflective structures overlap with the contact pads over an overlap distance at each side.

7. The device of claim 6, wherein the overlap distance is between 500 nm to 5 micron.

8. The device of claim 1, wherein the reflective structures comprise gold, silver, or substantially aluminum, wherein the contact pads comprise substantially gold, and wherein the metal lines in the uppermost metal level comprise substantially copper, or aluminum.

9. The device of claim 1, further comprising amorphous semiconductor structures disposed between the reflective structures and the upper metal level.

10. The device of claim 9, wherein the amorphous semiconductor structures have a thickness of 0.2 micron to 1 micron.

11. The device of claim 9, wherein the amorphous semiconductor structures comprise amorphous silicon, or fluorinated amorphous silicon.

12. A semiconductor device comprising:

an uppermost metal level comprising metal lines, the uppermost metal level disposed over a semiconductor substrate;

contact pads disposed at a major surface of the semiconductor device, the contact pads coupled to the metal lines in the uppermost metal level; and

light absorptive structures disposed between the upper metal level and the contact pads, wherein the light absorptive structures comprise an amorphous semiconductor material.

13. The device of claim 12, further comprising:

a contact via coupled between the one of the metal lines in the uppermost metal level to one of the contact pads; and

a sidewall spacer electrically isolating the contact via from the light absorptive structures.

14. The device of claim 12, wherein the light absorptive structures are aligned with an isolation region separating the contact pads, wherein each one of the light absorptive structures is disposed directly under an associated portion of the isolation region.

15. The device of claim 12, wherein the light absorptive structures have a thickness of 0.2 micron to 1 micron.

16. The device of claim 12, wherein the amorphous semiconductor material comprises amorphous silicon or fluorinated amorphous silicon.

17. The device of claim 12, further comprising reflective structures disposed between the upper metal level and the contact pads, wherein the reflective structures are aligned to be directly under gaps between adjacent contact pads.

18. The device of claim 17, wherein the reflective structures partially overlap with the contact pads, wherein the reflective structure comprises a different metal than the contact pads and the metal lines in the uppermost metal level.