THREE-DIMENSIONAL RESISTIVE MEMORY AND METHOD OF FORMING THE SAME
First Claim
1. A three-dimensional resistive memory, comprising:
- a channel pillar, disposed on a substrate;
a first gate pillar, disposed on the substrate and at a first side of the channel pillar;
a first gate dielectric layer, disposed between the channel pillar and the first gate pillar;
a first stacked structure and a second stacked structure, disposed on the substrate and respectively at opposite second and third sides of the channel pillar, wherein each of the first stacked structure and the second stacked structure comprises a plurality of conductive material layers and a plurality of insulating material layers alternately stacked;
a variable resistance pillar, disposed on the substrate and at a side of the first stacked structure opposite to the channel pillar; and
an electrode pillar, disposed on the substrate and located inside of the variable resistance pillar.
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Accused Products
Abstract
Provided is a three-dimensional resistive memory including a channel pillar, a first gate pillar, a first gate dielectric layer, first and second stacked structures, a variable resistance pillar and an electrode pillar. The channel pillar is on a substrate. The first gate pillar is on the substrate and at a first side of the channel pillar. The first gate dielectric layer is between the channel pillar and the first gate pillar. The first and second stacked structures are on the substrate and respectively at opposite second and third sides of the channel pillar. Each of the first and second stacked structures includes conductive material layers and insulating material layers alternately stacked. The variable resistance pillar is on the substrate and at a side of the first stacked structure opposite to the channel pillar. The electrode pillar is on the substrate and inside of the variable resistance pillar.
22 Citations
23 Claims
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1. A three-dimensional resistive memory, comprising:
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a channel pillar, disposed on a substrate; a first gate pillar, disposed on the substrate and at a first side of the channel pillar; a first gate dielectric layer, disposed between the channel pillar and the first gate pillar; a first stacked structure and a second stacked structure, disposed on the substrate and respectively at opposite second and third sides of the channel pillar, wherein each of the first stacked structure and the second stacked structure comprises a plurality of conductive material layers and a plurality of insulating material layers alternately stacked; a variable resistance pillar, disposed on the substrate and at a side of the first stacked structure opposite to the channel pillar; and an electrode pillar, disposed on the substrate and located inside of the variable resistance pillar. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A three-dimensional resistive memory, comprising:
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a stacked structure, disposed on the substrate and having a line portion and a protruding portion perpendicular to each other, wherein the stacked structure comprises a plurality of conductive material layers and a plurality of insulating material layers alternately stacked; a first gate pillar, disposed on the substrate and at a first side of the protruding portion; a first gate dielectric layer, disposed between the protruding portion and the first gate pillar; a variable resistance pillar, disposed on the substrate and at a side of the protruding portion opposite to the line portion; and an electrode pillar, disposed on the substrate and located inside of the variable resistance pillar. - View Dependent Claims (13)
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14. A method of forming a three-dimensional resistive memory, comprising:
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forming a stacked structure on a substrate, wherein the stacked structure comprises a plurality of conductive material layers and a plurality of insulating material layers alternately stacked; removing a portion of the stacked structure to expose the substrate and therefore form a first stacked portion and a second stacked portion connected to each other, wherein an extension direction of the first stacked portion is perpendicular to an extension direction of the second stacked portion; forming a first insulating layer on the substrate aside the first stacked portion and the second stacked portion; removing a portion of the first insulating layer to expose the substrate and therefore form a first opening, wherein the first opening is located at one side of the second stacked portion and separated from the second stacked portion with the first insulating layer; forming a first gate material layer in the first opening; removing another portion of the first insulating layer to form a second opening, wherein the second stacked portion is located between the first stacked portion and the second opening; and sequentially forming a variable resistance layer and an electrode material layer on a sidewall of the second opening. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification