METHOD OF PRODUCING SEMICONDUCTOR CHIPS

• US 20170271438A1
• Filed: 06/06/2017
• Published: 09/21/2017
• Est. Priority Date: 02/16/2011
• Status: Active Grant

• Current Assignee: OSRAM OLED GMBH (Ams-Osram AG)
• Original Assignee: Osram Opto Semiconductors GmbH (Ams-Osram AG)
• Inventors: Gnther, Ewald Karl Michael, Plssl, Andreas, Zull, Heribert, Veit, Thomas, Kmpf, Mathias, Dennemarck, Jens, Bhm, Bernd, Perzlmaier, Korbinian
• Granted Patent: US 10,224,393 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/14 including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation radiation-sensitive components structurally associated with one or more electric light sources only H01L31/14; couplings of light guides with optoelectronic elements G02B6/42
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/66128 Planar diodes
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body
• CPC Class Codes: H01L 33/641 characterized by the materials

Abstract

A method of producing a plurality of semiconductor chips includes a) providing a carrier substrate having a first major face and a second major face opposite the first major face; b) forming a diode structure between the first major face and the second major face, the diode structure electrically insulating the first major face from the second major face at least with regard to one polarity of an electrical voltage; c) arranging a semiconductor layer sequence on the first major face of the carrier substrate; and d) singulating the carrier substrate with the semiconductor layer sequence into a plurality of semiconductor chips.

Claims

1. A method of producing a plurality of semiconductor chips comprising:

a) providing a carrier substrate having a first major face and a second major face opposite the first major face;

b) forming a diode structure between the first major face and the second major face, said diode structure electrically insulating the first major face from the second major face at least with regard to one polarity of an electrical voltage;

c) arranging a semiconductor layer sequence on the first major face of the carrier substrate; and

d) singulating the carrier substrate with the semiconductor layer sequence into a plurality of semiconductor chips.

2. The method according to claim 1, wherein b) is carried out before d).

3. The method according to claim 1, wherein b) is carried out after d).

4. The method according to claim 1, wherein the diode structure is formed by full-surface doping of the carrier substrate.

5. The method according to claim 1, wherein the semiconductor layer sequence is deposited on a growth substrate and the growth substrate is removed after c).

6. The method according to claim 1, wherein the semiconductor layer sequence is bonded to the carrier substrate.

7. The method according to claim 1, wherein the semiconductor layer sequence is deposited epitaxially on the carrier substrate in b).

8. The method according to claim 1, wherein the semiconductor layer sequence is removed in places to expose the first major face.

9. The method according to claim 1, wherein the diode structure comprises a first diode and a second diode, the first diode and the second diode being oppositely oriented with respect to their conducting direction.

10. The method according to claim 1, wherein the diode structure is formed by layered doping of the carrier substrate.

11. The method according to claim 1, wherein the diode structure comprises at least three successive layers configured alternately with respect to their conduction type.

12. The method according to claim 1, wherein a side face of the carrier substrate is provided with a passivation layer.

13. The method according to claim 1, wherein a protection diode is formed in the carrier substrate.

14. The method according to claim 13, wherein the protection diode is formed between the first major face and the diode structure.