Bipolar Semiconductor Device Having Localized Enhancement Regions

• US 20170271445A1
• Filed: 03/18/2016
• Published: 09/21/2017
• Est. Priority Date: 03/18/2016
• Status: Abandoned Application

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Inventors: Udrea, Florin, Camuso, Gianluca, Hsieh, Alice Pei-Shan, Ng, Chiu, Tang, Yi, Vytla, Rajeev Krishna, Li, Canhua
• Application Number:
  US15/073,937
• Publication Number:
  US 20170271445A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

There are disclosed herein various implementations of a bipolar semiconductor device having localized enhancement regions. Such a bipolar semiconductor device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type opposite the first conductivity type. The bipolar semiconductor device also includes a first control trench extending through an inversion region having the second conductivity type, and further extending into the drift region, the first control trench being adjacent to cathode diffusions. In addition, the bipolar semiconductor device includes first and second depletion trenches, each having a depletion electrode, the first depletion trench being situated between the second depletion trench and the first control trench. An enhancement region having the first conductivity type is localized in the drift region between the first and second depletion trenches. In one implementation, the bipolar semiconductor device may be an insulated-gate bipolar transistor (IGBT).

Claims

1. A bipolar semiconductor device comprising a plurality of unit cells, each of said plurality of unit cells comprising:

a drift region having a first conductivity type situated over an anode layer having a second conductivity type opposite said first conductivity type;

a first control trench extending through an inversion region having said second conductivity type, and further extending into said drift region, said first control trench adjacent to cathode diffusions;

first and second depletion trenches, each having a depletion electrode;

said first depletion trench being situated between said second depletion trench and said first control trench;

an enhancement region having said first conductivity type localized in said drift region between said first and second depletion trenches, so that said enhancement region is not situated adjacent said first control trench or between said first depletion trench and said first control trench.

2. The bipolar semiconductor device of claim 1, wherein said enhancement region adjoins said first and second depletion trenches.

3. The bipolar semiconductor device of claim 1, wherein a doping concentration of said enhancement region is greater than a doping concentration of said drift region.

4. The bipolar semiconductor device of claim 1, wherein a doping concentration of said enhancement region is less than a doping concentration of said cathode diffusions.

5. The bipolar semiconductor device of claim 1, wherein said depletion electrodes are electrically coupled to said cathode diffusions.

6. The bipolar semiconductor device of claim 1, wherein each of said plurality of unit cells further comprises a buffer layer having said first conductivity type situated between said anode layer and said drift region.

7. The bipolar semiconductor device of claim 1, wherein said first conductivity is N type and said second conductivity is P type.

8. The bipolar semiconductor device of claim 1, wherein each of said plurality of unit cells further comprises a second control trench, said first control trench situated between said second control trench and said first and second depletion trenches.

9. The bipolar semiconductor device of claim 1, wherein each of said plurality of unit cells further comprises a third depletion trench adjacent to said first and second depletion trenches, wherein said second depletion trench is situated between said third depletion trench and said first depletion trench, wherein said enhancement region is localized in said drift region between said first, second, and third depletion trenches.

10. The bipolar semiconductor device of claim 9, wherein each of said plurality of unit cells further comprises a second control trench, said first control trench situated between said second control trench and said first, second, and third depletion trenches.

21. The bipolar semiconductor device of claim 6, wherein said enhancement region adjoins said inversion region and is spaced apart from said buffer layer by said drift region.

11. An insulated-gate bipolar transistor (IGBT) comprising a plurality of IGBT unit cells, each of said plurality of IGBT unit cells comprising:

a drift region having a first conductivity type situated over a collector having a second conductivity type opposite said first conductivity type;

a first gate trench extending through a base having said second conductivity type, and further extending into said drift region, said gate trench adjacent to emitter diffusions;

first and second depletion trenches, each having a depletion electrode;

said first depletion trench being situated between said second depletion trench and said first gate trench;

an enhancement region having said first conductivity type localized in said drift region between said first and second depletion trenches, so that said enhancement region is not situated adjacent said first gate trench or between said first depletion trench and said first gate trench.

12. The IGBT of claim 11, wherein said enhancement region adjoins said first and second depletion trenches.

13. The IGBT of claim 11, wherein a doping concentration of said enhancement region is greater than a doping concentration of said drift region.

14. The IGBT of claim 11, wherein a doping concentration of said enhancement region is less than a doping concentration of said emitter diffusions.

15. The IGBT of claim 11, wherein said depletion electrodes are electrically coupled to said emitter diffusions.

16. The IGBT of claim 11, wherein each of said plurality of IGBT unit cells further comprises a buffer layer having said first conductivity type situated between said collector and said drift region.

17. The IGBT of claim 11, wherein said first conductivity is N type and said second conductivity is P type.

18. The IGBT of claim 11, wherein each of said plurality of IGBT unit cells further comprises a second gate trench, said first gate trench situated between said second gate trench and said first and second depletion trenches.

19. The IGBT of claim 11, wherein each of said plurality of IGBT unit cells further comprises a third depletion trench adjacent to said first and second depletion trenches, wherein said second depletion trench is situated between said third depletion trench and said first depletion trench, wherein said enhancement region is localized in said drift region between said first, second, and third depletion trenches.

20. The IGBT of claim 19, wherein each of said plurality of IGBT unit cells further comprises a second gate trench, said first gate trench situated between said second gate trench and said first, second, and third depletion trenches.

22. The IGBT of claim 16, wherein said enhancement region adjoins said base and is spaced apart from said buffer layer by said drift region.