RADIO FREQUENCY (RF) SWITCH WITH ON AND OFF SWITCHING ACCELERATION

• US 20170272066A1
• Filed: 05/03/2017
• Published: 09/21/2017
• Est. Priority Date: 01/08/2016
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Scott, Baker, Maxim, George, Oshima, Hideya, Leipold, Dirk Robert Walter, Bolton, Eric K., Kerr, Daniel Charles
• Granted Patent: US 10,044,349 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/161 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

A Radio Frequency (RF) switch having two or more stages coupled in series is disclosed. A first Field-Effect Transistor (FET) with a first control terminal is coupled across a gate resistor to shunt the gate resistor when the first FET is on. An RF switching device is configured to pass an RF signal between a signal input and a signal output when the RF switching device is on. A second FET having a second control terminal coupled to an acceleration output is configured to shunt the RF switching device when the second FET is on. A third FET is coupled between the first control terminal and the signal input for controlling charge on a gate of the first FET. A third control terminal of the third FET is coupled to an acceleration input for controlling an on/off state of the third FET.

Claims

1. A radio frequency (RF) switch comprising:

two or more stages coupled in series between an RF input terminal and an RF output terminal, each stage comprising;

a gate resistor coupled between a control input and a control output;

a first field-effect transistor (FET) having a first current terminal coupled to the control input and a second current terminal coupled to the control output to shunt the gate resistor when the first FET is on, and a first control terminal for controlling an on/off state of the first FET;

an RF switching device having a third current terminal coupled to a signal input, a fourth current terminal coupled to a signal output to pass an RF signal between the signal input and the signal output when the RF switching device is on, and a second control terminal coupled to the control output for controlling an on/off state of the RF switching device;

a second FET having a fifth current terminal coupled to the signal input and a sixth current terminal coupled the signal output to shunt the RF switching device when the second FET is on, and a third control terminal coupled to an acceleration output for controlling an on/off state of the second FET; and

a third FET having a seventh current terminal coupled to the first control terminal of the first FET, an eighth current terminal coupled to the signal input for controlling charge on a gate of the first FET, and a fourth control terminal coupled to an acceleration input for controlling an on/off state of the third FET.

2. The RF switch of claim 1 further comprising an anticipated control signal generator having a gate control input for receiving a gate signal that controls the on/off state of the RF switching device, and an anticipated control signal output coupled to the acceleration input, wherein the anticipated control signal generator is configured to generate an anticipated control signal from the gate signal and output the anticipated control signal to the acceleration input before the gate signal arrives at the control input of the two or more stages.

3. The RF switch of claim 2 wherein the anticipated control signal generator is further configured to ramp a voltage level of the anticipated control signal from an off voltage of the first FET, the second FET, and the third FET to a ground voltage at a first slope and from the ground voltage through an on voltage to a peak on voltage of the first FET, the second FET, and the third FET at a second slope that is less than the first slope in response to a turn-on transition of the gate signal.

4. The RF switch of claim 3 wherein the anticipated control signal generator is further configured to lower the anticipated control signal from the peak on voltage to the ground voltage at a third slope having a magnitude greater than the second slope once the gate signal has turned on the RF switching device.

5. The RF switch of claim 4 wherein the anticipated control signal generator is further configured to ramp the anticipated control signal from the ground voltage through the on voltage to the peak on voltage at a fourth slope greater than the second slope in response to a turn-off transition of the gate signal.

6. The RF switch of claim 5 wherein the anticipated control signal generator is further configured to maintain the anticipated control signal at the peak on voltage for a predetermined time to drain charge from the gate of the first FET.

7. The RF switch of claim 6 wherein the anticipated control signal generator is further configured to ramp the anticipated control signal from the peak on voltage through the on voltage to the ground voltage once the turn-on transition of the gate signal is complete.

8. The RF switch of claim 7 wherein the anticipated control signal generator is further configured to ramp the anticipated control signal from ground voltage to off voltage once the gate signal has turned off the RF switching device.

9. The RF switch of claim 1 further comprising an acceleration resistor coupled between the acceleration input and the acceleration output.

10. The RF switch of claim 1 further comprising a drain-to-source resistor coupled between the signal input and the signal output.

11. The RF switch of claim 1 wherein the signal input of a first stage of the two or more stages is communicatively coupled to the RF input terminal, and the signal output of a last stage of the two or more stages is coupled to the RF output terminal.

12. The RF switch of claim 11 wherein the signal output of a proceeding stage of the two or more stages is coupled to the signal input of a following stage of the two or more stages.

13. The RF switch of claim 12 wherein the control output of the proceeding stage of the two or more stages is coupled to the control input of the following stage of the two or more stages.

14. The RF switch of claim 12 wherein the acceleration output of the proceeding stage of the two or more stages is coupled to the acceleration input of the following stage of the two or more stages.

15. The RF switch of claim 11 further comprising a lead RF switching device having a ninth current input terminal coupled to the RF input terminal, a tenth current input terminal coupled to the signal input of the first stage, and a fifth control terminal coupled to the control input of the first stage.

16. The RF switch of claim 15 further comprising a fourth FET having an eleventh current terminal coupled to the RF input terminal and a twelfth current terminal coupled to the signal input of the first stage, and a sixth control terminal coupled to the acceleration input of the first stage.

17. The RF switch of claim 2 further comprising a common gate resistor and a delay resistor coupled in series between a gate control terminal for receiving the gate signal and the signal input of a first stage of the two or more stages.

18. The RF switch of claim 17 wherein a resistance value of the delay resistor is selected to provide a time constant that causes the anticipated control signal to arrive at the acceleration input at least 400 ns before the gate signal arrives at the control input of the first stage.

19. The RF switch of claim 17 further comprising a fifth FET having a seventh control terminal for controlling an off/on state of the fifth FET, a thirteenth current terminal coupled to one end of the common gate resistor and a fourteenth current terminal coupled to another end of the common gate resistor such that the common gate resistor is shunted when the fifth FET is in an on state.

20. The RF switch of claim 19 wherein the fifth FET having the seventh control terminal is coupled to the anticipated control signal output of the anticipated control signal generator.

21. The RF switch of claim 19 further including a second anticipated control signal generator having a second gate control input for receiving the gate signal that controls the on/off state of the RF switching device, and a second anticipated control signal output coupled to the seventh control terminal, wherein the second anticipated control signal generator is configured to generate a second anticipated control signal from the gate signal and output the second anticipated control signal to the seventh control terminal before the gate signal arrives at the control input of the two or more stages.

22. A radio frequency (RF) switch comprising:

a gate resistor coupled to a control input;

a first field-effect transistor (FET) coupled across the gate resistor to shunt the gate resistor when the first FET is on, the first FET including a first control terminal;

an RF switching device having a control terminal coupled to the gate resistor and configured to pass an RF signal between a signal input and a signal output when the RF switching device is on;

a second FET having a second control terminal coupled to an acceleration output and coupled across the RF switching device to shunt the RF switching device when the second FET is on;

a third FET coupled between the first control terminal and the signal input for controlling charge on a gate of the first FET, wherein a third control terminal of the third FET is coupled to an acceleration input for controlling an on/off state of the third FET; and

an anticipated control signal generator having a gate control input for receiving a gate signal that controls the on/off state of the RF switching device, and an anticipated control signal output coupled to the acceleration input, wherein the anticipated control signal generator is configured to generate an anticipated control signal from the gate signal and output the anticipated control signal to the acceleration input before the gate signal arrives at the control input.