UNBALANCED MULTIPLEXER AND SCAN FLIP-FLOPS APPLYING THE SAME

• US 20170276729A1
• Filed: 10/24/2016
• Published: 09/28/2017
• Est. Priority Date: 03/28/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, MIN-SU
• Granted Patent: US 10,436,836 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G01R 31/31858 Delay testing

Abstract

An unbalanced multiplexer and a scan flip-flop including the unbalanced multiplexer, wherein the unbalanced multiplexer includes a first transmission circuit transmitting a first input signal to an output terminal according to a logic state of a selection signal; and a second transmission circuit transmitting a second input signal to the output terminal according to the logic state of the selection signal. A delay characteristic of a first transmission path from a first input terminal to the output terminal along which the first input signal of the first transmission circuit is transmitted, and a delay characteristic of a second transmission path from a second input terminal to the output terminal along which the second input signal of the second transmission circuit is transmitted, are set differently.

Claims

1. An unbalanced multiplexer comprising:

a first transmission circuit comprising a first pull-up circuit connected between a source voltage terminal and an output terminal, and a first pull-down circuit connected between the output terminal and a ground voltage terminal, the first transmission circuit configured to complementarily apply a selection signal and a first input signal to the first pull-up circuit and the first pull-down circuit, and to transmit the first input signal to the output terminal according to a logic state of the selection signal; and

a second transmission circuit comprising a second pull-up circuit connected between the source voltage terminal and the output terminal, and a second pull-down circuit connected between the output terminal and the ground voltage terminal, the second transmission circuit configured to complementarily apply the selection signal and a second input signal to the second pull-up circuit and the second pull-down circuit, and to transmit the second input signal to the output terminal according to the logic state of the selection signal,

wherein a delay characteristic of a first transmission path from a first input terminal to the output terminal along which the first input signal of the first transmission circuit is transmitted, and a delay characteristic of a second transmission path from a second input terminal to the output terminal along which the second input signal of the second transmission circuit is transmitted, are set to be different.

2. The unbalanced multiplexer of claim 1, wherein a data signal is applied to the first input terminal as the first input signal, a scan input signal is applied to the second input terminal as the second input signal, the selection signal is a scan enable signal, and the second transmission path is configured to have a delay time that is greater than a delay time of the first transmission path.

3. The unbalanced multiplexer of claim 1, wherein the first pull-up circuit comprises first group p-type metal-oxide-semiconductor (PMOS) transistors connected between the source voltage terminal and the output terminal in a cascode structure, the first pull-down circuit comprises second group n-type metal-oxide-semiconductor (NMOS) transistors connected between the output terminal and the ground voltage terminal in the cascode structure, the second pull-up circuit comprises third group PMOS transistors connected between the source voltage terminal and the output terminal in the cascode structure, and the second pull-down circuit comprises fourth group NMOS transistors connected between the output terminal and the ground voltage terminal in the cascode structure,

wherein the selection signal is a scan enable signal that is applied to a gate of one of the first group PMOS transistors, an inverted scan enable signal is applied to a gate of one of the second group NMOS transistors, and the first input signal is a data signal that is applied to a gate of each of the first group PMOS transistors other than the one of the first group PMOS transistors and each of the second group NMOS transistors other than the one of the second group NMOS transistors,

wherein the inverted scan enable signal is applied to a gate of one of the third group PMOS transistors, the scan enable signal is applied to a gate of one of the fourth group NMOS transistors, and the second input signal is a scan input signal that is applied to a gate of each of the third group PMOS transistors other than the one of the third group PMOS transistors and each of the fourth group NMOS transistors other than the one of the fourth group NMOS transistors, and

wherein the second pull-up circuit or the second pull-down circuit is configured to have a delay time when the scan input signal is transmitted to the output terminal through the second pull-up circuit or the second pull-down circuit that is greater than a delay time when the data signal is transmitted to the output terminal through the first pull-up circuit or the first pull-down circuit.

4. The unbalanced multiplexer of claim 3, wherein a number of transistors having gates to which the scan input signal is applied from among the third group PMOS transistors and the fourth group NMOS transistors is greater than a number of transistors having gates to which the data signal is applied from among the first group PMOS transistors and the second group NMOS transistors.

5. The unbalanced multiplexer of claim 4, wherein a number of the third group PMOS transistors having gates to which the scan input signal is applied is the same as a number of the fourth group NMOS transistors having gates to which the scan input signal is applied.

6. The unbalanced multiplexer of claim 4, wherein a number of the third group PMOS transistors having gates to which the scan input signal is applied and a number of the fourth group NMOS transistors having gates to which the scan input signal is applied are asymmetrically different from each other.

7. The unbalanced multiplexer of claim 4, wherein one of a number of the third group PMOS transistors having gates to which the scan input signal is applied and a number of the fourth group NMOS transistors having gates to which the scan input signal is applied is greater than the other.

8. The unbalanced multiplexer of claim 3, wherein a number of the first group PMOS transistors and a number of the third group PMOS transistors are the same, a number of the second group NMOS transistors and a number of the fourth group NMOS transistors are the same, and a length of a gate of at least one of the third group PMOS transistors or the fourth group NMOS transistors is greater than a length of a gate of each of the first group PMOS transistors and the second group NMOS transistors.

9. The unbalanced multiplexer of claim 3, wherein a number of the first group PMOS transistors and a number of the third group PMOS transistors are the same, a number of the second group NMOS transistors and a number of the fourth group NMOS transistors are the same, and at least one of the third group PMOS transistors or the fourth group NMOS transistors is configured to have a threshold voltage higher than a threshold voltage of each of the first group PMOS transistors and the second group NMOS transistors.

10. A scan flip-flop comprising:

a multiplexer comprising a first input terminal, a second input terminal, and a selection terminal, and configured to transmit a signal input to one of the first input terminal and the second input terminal to a first node according to a logic state of a selection signal applied to the selection terminal; and

a latch circuit configured to latch the signal transmitted to the first node in response to a clock signal and to output the latched signal to an output terminal,

wherein a delay characteristic of a first transmission path from the first input terminal to the first node and a delay characteristic of a second transmission path from the second input terminal to the first node are set to be different.

11. The scan flip-flop of claim 10, wherein a data signal is applied to the first input terminal, a scan input signal is applied to the second input terminal, a scan enable signal is applied to the selection terminal as the selection signal, and the multiplexer is configured so that a delay time of the second transmission path is greater than a delay time of the first transmission path.

12. The scan flip-flop of claim 11, wherein the first transmission path in the multiplexer comprises first group PMOS transistors connected between a source voltage terminal and the first node in a cascode structure, and second group NMOS transistors connected between the first node and a ground voltage terminal in the cascode structure,

wherein the second transmission path in the multiplexer comprises third group PMOS transistors connected between the source voltage terminal and the first node in the cascode structure, and fourth group NMOS transistors connected between the first node and the ground voltage terminal in the cascode structure,

wherein the scan enable signal is applied to a gate of one of the first group PMOS transistors, an inverted scan enable signal is applied to a gate of one of the second group NMOS transistors, and the data signal is applied to a gate of each of the first group PMOS transistors other than the one of the first group PMOS transistors and each of the second group NMOS transistors other than the one of the second group NMOS transistors,

wherein the inverted scan enable signal is applied to a gate of one of the third group PMOS transistors, the scan enable signal is applied to a gate of one of the fourth group NMOS transistors, and the scan input signal is applied to a gate of each of the third group PMOS transistors other than the one of the third group PMOS transistors and each of the fourth group NMOS transistors other than the one of the fourth group NMOS transistors, and

wherein a number of transistors having gates to which the scan input signal is applied from among the third group PMOS transistors and the fourth group NMOS transistors is greater than a number of transistors having gates to which the data signal is applied from among the first group PMOS transistors and the second group NMOS transistors.

13. The scan flip-flop of claim 11, wherein the first transmission path in the multiplexer comprises first group PMOS transistors connected between a source voltage terminal and the first node in a cascode structure, and second group NMOS transistors connected between the first node and a ground voltage in the cascode structure,

wherein the second transmission path of the multiplexer comprises third group PMOS transistors connected between the source voltage terminal and the first node in the cascode structure, and fourth group NMOS transistors connected between the first node and the ground voltage terminal in the cascode structure,

wherein the scan enable signal is applied to a gate of one of the first group PMOS transistors, an inverted scan enable signal is applied to a gate of one of the second group NMOS transistors, and the data signal is applied to a gate of each of the first group PMOS transistors other than the one of the first group PMOS transistors and each of the second group NMOS transistors other than the one of the second group NMOS transistors,

wherein the inverted scan enable signal is applied to a gate of one of the third group PMOS transistors, the scan enable signal is applied to a gate of one of the fourth group NMOS transistors, and the scan input signal is applied to a gate of each of the third group PMOS transistors other than the one of the third group PMOS transistors and each of the fourth group NMOS transistors other than the one of the fourth group NMOS transistors,

wherein a number of transistors having gates to which the data signal is applied from among the first group PMOS transistors and the second group NMOS transistors is the same as a number of transistors having gates to which the scan input signal is applied from among the third group PMOS transistors and the fourth group NMOS transistors, and

wherein at least one of the third PMOS transistors or the fourth NMOS transistors are configured to have a threshold voltage that is higher than a threshold voltage of each of the first group PMOS transistors and the second group NMOS transistors.

14. The scan flip-flop of claim 10, wherein the latch circuit comprises:

a first tri-state inverter configured to invert a signal at the first node and to output a first inverted signal to a second node when an inverted clock signal is in a logic high state;

a first inverter configured to invert a signal at the second node and to output a second inverted signal to a third node;

a second tri-state inverter configured to invert a signal at the third node and to output a third inverted signal to the second node when a clock signal is in the logic high state;

a transmission gate configured to transfer the signal at the third node to a fourth node when the clock signal is in the logic high state;

a second inverter configured to invert a signal at the fourth node and to output a fourth inverted signal to a fifth node;

a third tri-state inverter configured to invert a signal at the fifth node and to output a fifth inverted signal to the fourth node when the inverted clock signal is in the logic high state; and

a third inverter configured to invert the signal at the fourth node and to output the latched signal to the output terminal.

15. The scan flip-flop of claim 10, wherein the latch circuit comprises:

a first inverter configured to invert a clock signal at a clock terminal and to output an inverted clock signal to a second node;

a first tri-state inverter configured to invert a signal at the first node and to output a first inverted signal to a third node when a signal at the second node is in a logic high state;

a second inverter configured to invert a signal at the third node and to output a second inverted signal to a fourth node;

a second tri-state inverter configured to invert a signal at the fourth node and to output a third inverted signal to the third node when the clock signal at the clock terminal is in the logic high state;

a transmission gate configured to transfer the signal at the fourth node to a fifth node when the clock signal at the clock terminal is in the logic high state;

a third inverter configured to invert a signal at the fifth node and to output a fourth inverted signal to a sixth node;

a third tri-state inverter configured to invert a signal at the sixth node and to output a fifth inverted signal to the fifth node when the signal at the second node is in the logic high state; and

a fourth inverter configured to invert the signal at the fifth node and to output the latched signal to the output terminal.

16. An unbalanced multiplexer comprising:

a first transmission circuit configured to transmit a first signal along a first transmission path from a first input terminal to an output terminal according to a logic state of a selection signal; and

a second transmission circuit configured to transmit a second signal along a second transmission path from a second input terminal to the output terminal according to the logic state of the selection signal,

wherein the first transmission path is configured to have a delay characteristic that is set to be different than a delay characteristic of the second transmission path.

17. The unbalanced multiplexer of claim 16, wherein the first transmission path comprises first group p-type metal-oxide-semiconductor (PMOS) transistors in a cascode arrangement connected to second group n-type metal-oxide-semiconductor (NMOS) transistors in a cascode arrangement, and

the second transmission path comprises third group PMOS transistors in a cascode arrangement connected to fourth group NMOS transistors in a cascode arrangement.

18. The unbalanced multiplexer of claim 17, wherein at least one of a number of transistors in the third group PMOS transistors and a number of transistors in the fourth group NMOS transistors is greater than a number of transistors in the first group PMOS transistors and a number of transistors in the second group NMOS transistors.

19. The unbalanced multiplexer of claim 17, wherein a number of transistors in the first group PMOS transistors, a number of transistors in the second group NMOS transistors, a number of transistors in the third group PMOS transistors and a number of transistors in the fourth group NMOS transistors are the same, and

a length of a gate of at least one of the transistors in the third group PMOS transistors and a length of a gate in at least one of the transistors in the fourth group NMOS transistors are greater than a length of each of the transistors in the first group PMOS transistors and in the second group NMOS transistors.

20. The unbalanced multiplexer of claim 17, wherein a number of transistors in the first group PMOS transistors, a number of transistors in the second group NMOS transistors, a number of transistors in the third group PMOS transistors and a number of transistors in the fourth group NMOS transistors are the same, and

a threshold voltage of at least one of the transistors in the third group PMOS transistors and a threshold voltage of at least one of the transistors in the fourth group NMOS transistors are greater than a threshold voltage of each of the transistors in the first group PMOS transistors and in the second group NMOS transistors.