MEMORY DEVICE AND OPERATING METHOD THEREOF

• US 20170277454A1
• Filed: 08/23/2016
• Published: 09/28/2017
• Est. Priority Date: 03/23/2016
• Status: Abandoned Application

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: SHIN, Beom Ju
• Application Number:
  US15/244,641
• Publication Number:
  US 20170277454A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

Provided herein are a memory device and an operating method thereof. The memory device includes: a memory device comprising: a memory cell array including a plurality of pages; a peripheral circuit suitable for successively receiving a plurality of logical page data, and performing a program operation with the received logical page data to a selected page; and a control logic suitable for controlling the peripheral circuit to perform, in parallel, the program operation to the selected page with reception-completed logical page data among the plurality of logical page data while receiving other logical page data.

Claims

1. A memory device comprising:

a memory cell array including a plurality of pages;

a peripheral circuit suitable for successively receiving a plurality of logical page data, and performing a program operation with the received logical page data to a selected page; and

a control logic suitable for controlling the peripheral circuit to perform, in parallel, the program operation to the selected page with reception-completed logical page data among the plurality of logical page data while receiving other logical page data.

2. The memory device according to claim 1,

wherein the control logic further monitors a state of receiving the respective logical page data, and

wherein the control logic controls the peripheral circuit to perform the program operation to the selected page with the reception-completed logical page data according to a result of the monitoring.

3. The memory=device according to claim 1, wherein the control logic comprises:

a data-transmission-completion signal output unit suitable for monitoring a state of receiving the respective logical page data and outputting one of transmission-completion signals respectively corresponding to the plurality of logical page data depending on a result of the monitoring;

an operation control unit suitable for outputting a program operation signal and a ready signal in response to the outputted one of the transmission-completion signals;

a program control unit suitable for outputting program control signals for controlling the peripheral circuit to perform the program operation to the selected page with the reception-completed logical page data in response to the program operation signal; and

a ready/bush signal output unit suitable for outputting a ready/busy signal to a memory controller in response to the ready signal.

4. The memory device according to claim 3, wherein, when reception of one of the plurality of logical page data is determined to be completed according to the result of the monitoring, the data transmission-completion signal output unit outputs one of the transmission-completion signals corresponding to the reception-completed logical page.

5. The memory device according to claim 3, wherein the operation control unit keeps outputting the program operation signal in response to a firstly provided one of the transmission-completion signals.

6. The memory device according to claim 3, wherein the operation control unit outputs the ready signal until all of the transmission-completion signals are provided.

7. The memory device according to claim 1, wherein the peripheral circuit includes page buffers suitable for receiving the logical page data.

8. The memory device according to claim 7, wherein the control logic further monitors a state of receiving the respective logical page data using the logical page data provided to the page buffers.

9. The memory device according to claim 1,

wherein the memory cell array comprises a plurality of planes each of which includes a plurality of memory blocks,

wherein each of the memory blocks includes a plurality of pages.

10. The memory device according to claim 9,

wherein the control logic further monitors a state of receiving the logical page data to be programmed on selected ones of the planes, and

wherein the control logic controls the peripheral circuit to perform the program operation to the selected pages of the selected planes with the reception-completed logical page data according to a result of the monitoring.

11. An operating method of a memory device comprising:

receiving first to N_th logical page data;

performing a program operation to a selected page with reception-completed one among the first to N_th logical page data; and

receiving the other logical page data during the performing of the program operation with the reception-completed logical page data.

12. The operating method according to claim 11, further comprising performing the program operation to the selected page with the other logical page data after the performing of the program operation with the reception-completed logical page data and the receiving of the other logical page data.

13. An operating method of a memory device comprising:

receiving least significant bit (LSB) data, central significant bit (CSB) data and most significant bit (MSB) data;

performing a program operation to selected page with the LSB data, which is reception-completed;

receiving the CSB data and the MSB data during the performing of the program operation with the reception-completed LSB data; and

performing the program operation to the selected page with the CSB and MSB data after the performing of the program operation with the reception-completed LSB data and the receiving of the CSB and MSB data.

14. The operating method according to claim 13, wherein the performing of the program operation with the reception-completed LSB data comprises:

outputting an LSB-transmission-completion signal upon completion of receiving the LSB data;

outputting a program operation signal in response to the LSB-transmission-complete signal; and

outputting program control signals for performing the program operation to the selected page in response to the program operation signal.

15. Tie operating method according to claim 14, further comprising outputting a ready/busy signal when the program operation signal is outputted.

16. The operating method according to claim 15, wherein the ready/busy signal is output until completion of the receiving of all of the LSB data, the CSB data and the MSB data.

17. The operating method according to claim 13, wherein all of the CSB data and the MSB data are received before the program operation with the LSB data is completed.