EXTENDING THE USEFUL LIFESPAN OF NONVOLATILE MEMORY

• US 20170277629A1
• Filed: 03/25/2016
• Published: 09/28/2017
• Est. Priority Date: 03/25/2016
• Status: Abandoned Application

• Current Assignee: Alibaba Group Holding Ltd.
• Original Assignee: Alibaba Group Holding Ltd.
• Inventors: LI, Shu
• Application Number:
  US15/081,512
• Publication Number:
  US 20170277629A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A system for extending the useful lifespan of solid-state nonvolatile memory includes a memory that stores machine instructions and a processor coupled to the memory that executes the machine instructions to reconfigure a unit of nonvolatile memory cells from a first configuration that stores a minimum state, one of a group of intermediate states, or a maximum state as a current state to a second configuration that stores the minimum state, one of a subset of the group of intermediate states, or the maximum state as the current state.

Claims

1. A system for extending the useful lifespan of nonvolatile memory, comprising:

a memory that stores machine instructions; and

a processor coupled to the memory that executes the machine instructions to reconfigure a unit of nonvolatile memory cells from a first configuration that stores one current state selected from the group consisting of a first number of states to a second configuration that stores one current state selected from the group consisting of a second number of states, wherein the first number is larger than the second number.

2. The system of claim 1, wherein the processor further executes the machine instructions to reconfigure the unit from the first configuration that stores one current state selected from the group consisting of a minimum state, at least one intermediate state, and a maximum state to the second configuration that stores one current state selected from the group consisting of the minimum state and the maximum state.

3. The system of claim 2, wherein the minimum state corresponds to a minimum threshold voltage distribution and the maximum state corresponds to a maximum threshold voltage distribution, the minimum threshold voltage distribution and the maximum threshold voltage distribution corresponding to one selected from the group consisting of multi-level cell NAND flash memory or triple-level cell NAND flash memory.

4. The system of claim 1, wherein the processor further executes the machine instructions to register the unit of nonvolatile memory cells as a reconfigured unit in a flash translation layer, the unit of nonvolatile memory cells including a block of NAND flash memory cells in a solid-state drive.

5. The system of claim 1, wherein the processor further executes the machine instructions to register the unit of nonvolatile memory cells as a reconfigured unit in a flash translation layer.

6. The system of claim 1, wherein the processor further executes the machine instructions to monitor a condition associated with the unit of nonvolatile memory cells and select a solid-state drive including the unit of nonvolatile memory cells for continued use based the condition.

7. A method of extending the useful lifespan of nonvolatile memory, comprising:

reconfiguring a unit of nonvolatile memory cells from a first configuration that stores one current state selected from the group consisting of a first number of states to a second configuration that stores one current state selected from the group consisting of a second number of states, wherein the first number is larger than the second number.

8. The method of claim 7, wherein before the reconfiguring a threshold voltage associated with a memory cell of the unit of nonvolatile memory cells reading greater than a first predetermined voltage but less than a second predetermined voltage indicates a first intermediate state and after the reconfiguring the threshold voltage reading less than the second predetermined voltage indicates a minimum state.

9. The method of claim 7, wherein before the reconfiguring a threshold voltage associated with a memory cell of the unit of nonvolatile memory cells reading greater than a first predetermined voltage but less than a second predetermined voltage indicates a first intermediate state and after the reconfiguring the threshold voltage reading greater than the first predetermined voltage indicates a maximum state.

10. The method of claim 7, wherein reconfiguring the unit of nonvolatile memory cells further comprises reconfiguring the unit from the first configuration that stores one current state selected from the group consisting of a minimum state, a first intermediate state, a second intermediate state, and a maximum state to the second configuration.

11. The method of claim 7, wherein reconfiguring the unit of nonvolatile memory cells further comprises reconfiguring the unit from a third configuration that stores one current state selected from the group consisting of a minimum state, a first intermediate state, a second intermediate state, a third intermediate state, a fourth intermediate state, a fifth intermediate state, a sixth intermediate state, and a maximum state to the first configuration that stores one current state selected from the group consisting of the minimum state, a first intermediate state, a second intermediate state, and the maximum state.

12. The method of claim 7, wherein a minimum state corresponds to a minimum threshold voltage distribution and a maximum state corresponds to a maximum threshold voltage distribution.

13. The method of claim 12, wherein the first number of states correspond to one selected from the group consisting of multi-level cell NAND flash memory or triple-level cell NAND flash memory.

14. The method of claim 7, wherein reconfiguring the unit of nonvolatile memory cells further comprises disregarding at least one intermediate state.

15. The method of claim 7, wherein the reconfiguring a unit of nonvolatile memory cells further comprises reassigning a discrete value associated with a maximum state.

16. The method of claim 7, wherein a minimum state corresponds to an erased state.

17. The method of claim 16, further comprising programming a maximum state from the erased state after the reconfiguring in a single step.

18. The method of claim 7, wherein the unit of nonvolatile memory cells includes a block of NAND flash memory cells in a solid-state drive.

19. The method of claim 7, further comprising:

monitoring a condition associated with the unit of nonvolatile memory cells; and

selecting a solid-state drive including the unit of nonvolatile memory cells for continued use based the condition.

20. A computer program product for extending the useful lifespan of nonvolatile memory, comprising:

a non-transitory, computer-readable storage medium encoded with instructions adapted to be executed by a processor to implement;

reconfiguring a unit of nonvolatile memory cells from a first configuration that stores one current state selected from the group consisting of a first number of states to a second configuration that stores one current state selected from the group consisting of a second number of states wherein the first number is larger than the second number.