FAN-OUT SEMICONDUCTOR PACKAGE

• US 20170278766A1
• Filed: 02/23/2017
• Published: 09/28/2017
• Est. Priority Date: 03/25/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: KIM, Eun Sil, LEE, Doo Hwan, BYUN, Dae Jung, KO, Tae Ho, KIM, Yeong A.
• Granted Patent: US 10,276,467 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/215 Material
• CPC Class Codes: H01L 2224/221 Disposition
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 23/295 containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10252 : Germanium [Ge]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/14335 : Digital signal processor [DSP]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/186 : Material
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A fan-out semiconductor package includes: a fan-out semiconductor package may include: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a reinforcing layer disposed on the encapsulant. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip.

Claims

1. A fan-out semiconductor package comprising:

a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip;

a first interconnection member disposed on the active surface of the semiconductor chip; and

a reinforcing layer disposed on the encapsulant,

wherein the first interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chip.

2. The fan-out semiconductor package of claim 1, wherein the reinforcing layer has an elastic modulus greater than that of the encapsulant.

3. The fan-out semiconductor package of claim 1, wherein the reinforcing layer has a coefficient of thermal expansion lower than that of the encapsulant.

4. The fan-out semiconductor package of claim 1, wherein the reinforcing layer includes a core material, an inorganic filler, and an insulating resin.

5. The fan-out semiconductor package of claim 4, further comprising a resin layer disposed on the reinforcing layer,

wherein the resin layer includes an inorganic filler and an insulating resin.

6. The fan-out semiconductor package of claim 5, further comprising openings penetrating through the resin layer, the reinforcing layer, and the encapsulant.

7. The fan-out semiconductor package of claim 5, further comprising a passivation layer disposed on the first interconnection member,

wherein the passivation layer includes an inorganic filler and an insulating resin.

8. The fan-out semiconductor package of claim 7, wherein a composition of the resin layer and a composition of the passivation layer are the same as each other.

9. The fan-out semiconductor package of claim 4, wherein the encapsulant includes an inorganic filler and an insulating resin, and a weight percentage of the inorganic filler included in the reinforcing layer is greater than that of the inorganic filler included in the encapsulant.

10. The fan-out semiconductor package of claim 9, wherein a weight percentage of the inorganic filler included in one side of the reinforcing layer in contact with the encapsulant and a weight percentage of the inorganic filler included in the other side of the reinforcing layer opposing the one side in relation to the core material are different from each other.

11. The fan-out semiconductor package of claim 10, wherein a1<

a2<

a3, in which a1 is the weight percentage of the inorganic filler included in the encapsulant, a2 is the weight percentage of the inorganic filler included in the one side of the reinforcing layer in contact with the encapsulant, and a3 is the weight percentage of the inorganic filler included in the other side of the reinforcing layer opposing the one side.

12. The fan-out semiconductor package of claim 1, wherein the reinforcing layer includes an inorganic filler and an insulating resin and does not include a core material.

13. The fan-out semiconductor package of claim 12, wherein the encapsulant includes an inorganic filler and an insulating resin, and a weight percentage of the inorganic filler included in the reinforcing layer is greater than that of the inorganic filler included in the encapsulant.

14. The fan-out semiconductor package of claim 1, further comprising a passivation layer disposed on the first interconnection member,

wherein the passivation layer includes an inorganic filler and an insulating resin.

15. The fan-out semiconductor package of claim 14, wherein the first interconnection member includes an insulating layer including an inorganic filler and an insulating resin, and a weight percentage of the inorganic filler included in the passivation layer is greater than that of the inorganic filler included in the insulating layer of the first interconnection member.

16. The fan-out semiconductor package of claim 1, further comprising an insulating member having a through-hole,

wherein the semiconductor chip is disposed in the through-hole of the insulating member, and

wherein a boundary surface between the reinforcing layer and the encapsulant has curved portions bent toward spaces between inner walls of the through-hole and the semiconductor chip.

17. The fan-out semiconductor package of claim 16, wherein the reinforcing layer has a thickness greater than that a first portion of the encapsulant covering the insulating member and that of a second portion of the encapsulant covering the inactive surface of the semiconductor chip.

18. The fan-out semiconductor package of claim 1, further comprising a second interconnection member having a through-hole,

wherein the semiconductor chip is disposed in the through-hole of the second interconnection member, and

wherein the second interconnection member includes a first insulating layer, a first redistribution layer in contact with the first interconnection member and embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, and

the first and second redistribution layers are electrically connected to the connection pads.

19. The fan-out semiconductor package of claim 18, wherein the second interconnection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and

the third redistribution layer is electrically connected to the connection pads.

20. The fan-out semiconductor package of claim 19, wherein the second redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

21. The fan-out semiconductor package of claim 18, wherein a distance between the redistribution layer of the first interconnection member and the first redistribution layer is greater than that between the redistribution layer of the first interconnection member and the connection pad.

22. The fan-out semiconductor package of claim 18, wherein the first redistribution layer has a thickness greater than that of the redistribution layer of the first interconnection member.

23. The fan-out semiconductor package of claim 18, wherein a lower surface of the first redistribution layer is disposed on a level above a lower surface of the connection pad.

24. The fan-out semiconductor package of claim 1, further comprising a second interconnection member having a through-hole,

wherein the semiconductor chip is disposed in the through-hole of the second interconnection member, and

wherein the second interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and

the first to third redistribution layers are electrically connected to the connection pads.

25. The fan-out semiconductor package of claim 24, wherein the second interconnection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and

the fourth redistribution layer is electrically connected to the connection pads.

26. The fan-out semiconductor package of claim 24, wherein the first insulating layer has a thickness greater than that of the second insulating layer.

27. The fan-out semiconductor package of claim 24, wherein the third redistribution layer has a thickness greater than that of the redistribution layer of the first interconnection member.

28. The fan-out semiconductor package of claim 24, wherein the first redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

29. The fan-out semiconductor package of claim 24, wherein a lower surface of the third redistribution layer is disposed on a level below a lower surface of the connection pad.

30. The fan-out semiconductor package of claim 1, wherein a boundary surface between the encapsulant and the reinforcing layer has an approximately linear shape.

38. The fan-out semiconductor package of claim 1, further comprising an insulating member having a through-hole,

wherein the semiconductor chip is disposed in the through-hole of the insulating member.

39. The fan-out semiconductor package of claim 1, further comprising a second interconnection member having a through-hole,

wherein the semiconductor chip is disposed in the through-hole of the second interconnection member, and

wherein the second interconnection member includes an insulating layer, a first redistribution layer disposed on a first surface of the insulating layer, and a second redistribution layer disposed on a second surface of the insulating layer opposing the first surface of the insulating layer, and

the first and second redistribution layers are electrically connected to the connection pads.

31-37. -37. (canceled)