Integrated System and Method of Making the Integrated System

• US 20170278836A1
• Filed: 06/09/2017
• Published: 09/28/2017
• Est. Priority Date: 08/02/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kilger, Thomas
• Granted Patent: US 10,224,317 B2
• Time in Patent Office: Days
• CPC Class Codes: H01F 2027/2809 on stacked layers
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 27/29 Terminals; Tapping arrangements for signal inductances
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0237 Disposition of the redistribution layers
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/0362 Photolithography
• CPC Class Codes: H01L 2224/0381 Cleaning, e.g. oxide removal step, desmearing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 : Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05552 : in top view
• CPC Class Codes: H01L 2224/05639 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/08145 : the bodies being stacked
• CPC Class Codes: H01L 2224/11 : Manufacturing methods
• CPC Class Codes: H01L 2224/11005 : for aligning the bump connector, e.g. marks, spacers
• CPC Class Codes: H01L 2224/11312 : Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
• CPC Class Codes: H01L 2224/1132 : Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 : using preformed bumps
• CPC Class Codes: H01L 2224/1145 : Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11462 : Electroplating
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/12105 : Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16503 : comprising an intermetallic compound
• CPC Class Codes: H01L 2224/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/40227 : Connecting the strap to a bond pad of the item
• CPC Class Codes: H01L 2224/45014 : Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/484 : Connecting portions
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/4847 : the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73221 : Strap and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/82101 : by additive methods, e.g. direct writing
• CPC Class Codes: H01L 2224/82106 : by subtractive methods
• CPC Class Codes: H01L 2224/83801 : Soldering or alloying
• CPC Class Codes: H01L 2224/84 : using a strap connector
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/206 : Length ranges
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/165 : incorporating printed inductors
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.

Claims

1. A method for manufacturing an integrated device, the method comprising:

forming a first reconstitution wafer comprising first components;

forming a second reconstitution wafer comprising second components;

dicing the second reconstitution wafer into second packaged components, the second packaged components comprising the second components;

placing the second packaged components on a first main surface of the first reconstitution wafer; and

dicing the first reconstitution wafer into integrated devices, each integrated device comprising a first packaged component and a second packaged component.

2. The method of claim 1, further comprising:

placing an integrated device on a carrier;

bonding the integrated device to the carrier; and

encapsulating the integrated device.

3. The method of claim 1, further comprising disposing a first redistribution layer (RDL) on the first main surface of the first reconstitution wafer.

4. The method of claim 3, further comprising, before dicing the second reconstitution wafer, disposing a second RDL on a first main surface of the second reconstitution wafer, wherein placing the second packaged components on the first main surface of the first reconstitution wafer comprises placing the second packaged components with second RDL regions facing the first main surface of the first reconstitution wafer.

5. The method of claim 4, wherein the first packaged components comprise first fan-out areas having first bonding pads placed thereon, and wherein the second packaged components comprise second fan-out areas having second bonding pads placed thereon.

6. The method of claim 1, wherein placing the second packaged components on the first main surface of the first reconstitution wafers comprises bonding second bonding pads of the second packaged components to first bonding pads of the first reconstitution wafer.

7. The method of claim 1, further comprising forming an insulation layer between the second packaged components and the first reconstitution wafer.

8. The method of claim 7, wherein the insulation layer comprises a high dielectric strength material.

9. The method of claim 7, further comprising forming a magnetic material between the second packaged components and the first reconstitution wafer.

10. The method of claim 1, wherein the second packaged components comprise secondary windings, wherein the first packaged components comprise primary windings, and wherein each integrated device comprises a transformer formed by a primary winding and a secondary winding.

11. The method of claim 10, wherein the transformer is a coreless transformer.

12. The method of claim 1, wherein the second packaged components comprise second portions of primary windings and second portions of secondary windings, wherein the first packaged components comprise first portions of the primary windings and first portions of the secondary windings, and wherein each integrated device comprises a transformer formed by a primary winding and a secondary winding, the primary winding includes a first portion of the primary winding and a second portion of the primary winding and the secondary winding includes a first portion of the secondary winding and a second portion of the secondary winding.

13. The method of claim 12, wherein the transformer is a coreless transformer.

14. The method of claim 1, wherein each integrated device comprises the first packaged component, the second packaged component and a third packaged component.

15. The method of claim 1, further comprising:

forming a first RDL layer on the first reconstitution wafer, the first RDL layer providing bonding pads for the first components;

forming a second RDL layer on the second reconstitution wafer, the second RDL layer providing bonding pads for the second components, wherein, after dicing the second reconstitution wafer, the second packaged components comprises the second RDL layer and second bonding pads; and

bonding the second bonding pads of the second packaged components to the bonding pads for the first components.

16. A method for manufacturing an integrated device, the method comprising:

providing a first plurality of chips and a second plurality of chips;

forming a first reconstitution wafer by embedding the first plurality of chips in a first encapsulation material;

forming a first redistribution line (RDL) layer on the first reconstitution wafer, the first RDL layer covering the first plurality of chips and the first encapsulation material and providing first bonding pads for the first plurality of chips;

forming a second reconstitution wafer by embedding the second plurality of chips in a second encapsulation material;

forming a second RDL layer on the second reconstitution wafer, the second RDL layer covering the second plurality of chips and the second encapsulation material and providing second bonding pads for the second plurality of chips;

dicing the second reconstitution wafer into second encapsulated components, wherein, after the dicing, the second encapsulated components comprise the second plurality of chips surrounded by the second encapsulation material, and the second bonding pads;

after dicing the second reconstitution wafer, placing the second encapsulated components on the first RDL layer of the first reconstitution wafer;

bonding the second bonding pads of the second encapsulated components to the first bonding pads; and

after the bonding, dicing the first reconstitution wafer into integrated devices, each integrated device comprising one of the first encapsulated components and one of the second encapsulated components.

17. The method of claim 16, further comprising forming primary windings in the first RDL and secondary windings in the second RDL.

18. The method of claim 17, further comprising forming an insulation layer having a high dielectric strength between the second encapsulated components and the first reconstitution wafer.

19. The method of claim 16, further comprising forming a magnetic material between the second encapsulated components and the first reconstitution wafer.

20. The method of claim 16, wherein the first RDL comprises first portions of primary windings and first portions of secondary windings and wherein the second RDL comprises second portions of the primary windings and second portions of the secondary windings.

21. The method of claim 20, further comprising:

electrically connecting the first portions of the primary windings with the second portions of the primary windings;

electrically connecting the first portions of the secondary windings with the second portions of the secondary windings; and

forming an insulation layer having a high dielectric strength between the second encapsulated components and the first reconstitution wafer.

22. The method of claim 21, further comprising forming a magnetic material between the second encapsulated components and the first reconstitution wafer.

23. A method for manufacturing an integrated device, the method comprising:

providing a first reconstitution wafer that comprises a first plurality of chips embedded in a first encapsulation material;

forming a first redistribution line (RDL) layer on the first reconstitution wafer, the first RDL layer covering the first plurality of chips and the first encapsulation material and providing first bonding pads for the first plurality of chips;

providing a second reconstitution wafer that comprises a second plurality of chips embedded in a second encapsulation material;

forming a second RDL layer on the second reconstitution wafer, the second RDL layer covering the second plurality of chips and the second encapsulation material and providing second bonding pads for the second plurality of chips;

dicing the second reconstitution wafer into second encapsulated components, after the dicing, the second encapsulated components comprise the second plurality of chips surrounded by the second encapsulation material, and the second bonding pads;

after dicing the second reconstitution wafer, placing the second encapsulated components on the first RDL layer of the first reconstitution wafer;

bonding the second bonding pads of the second encapsulated components to the first bonding pads; and

after the bonding, dicing the first reconstitution wafer into integrated devices, each integrated device comprising one of the first encapsulated components and one of the second encapsulated components.

24. The method of claim 23, further comprising forming primary windings in the first RDL and secondary windings in the second RDL.

25. The method of claim 24, further comprising forming an insulation layer having a high dielectric strength between the second encapsulated components and the first reconstitution wafer.

26. The method of claim 23, further comprising forming a magnetic material between the second encapsulated components and the first reconstitution wafer.

27. The method of claim 23, wherein the first RDL comprises first portions of primary windings and first portions of secondary windings and wherein the second RDL comprises second portions of the primary windings and second portions of the secondary windings.

28. The method of claim 27, further comprising:

electrically connecting the first portions of the primary windings with the second portions of the primary windings;

electrically connecting the first portions of the secondary windings with the second portions of the secondary windings; and

forming an insulation layer having a high dielectric strength between the second encapsulated components and the first reconstitution wafer.

29. The method of claim 28, further comprising forming a magnetic material between the second encapsulated components and the first reconstitution wafer.