SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20170278860A1
• Filed: 09/12/2016
• Published: 09/28/2017
• Est. Priority Date: 03/23/2016
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: AOYAMA, Kenji
• Granted Patent: US 10,546,871 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A semiconductor memory device according to an embodiment comprises: a memory cell array region including a plurality of conductive layers that are electrically connected to a plurality of memory cells arranged in a first direction on a semiconductor substrate, the first direction intersecting a surface of the semiconductor substrate; a stepped part for contacting the plurality of conductive layers to a wiring line; a contact extending in the first direction and being connected to the conductive layer in the stepped part; and a plurality of columnar bodies extending in the first direction and penetrates the conductive layer in the stepped part and including a first columnar body having a first height and a second columnar body having a second height which is lower than the first height.

Claims

1. A semiconductor memory device, comprising:

a memory cell array region including a plurality of conductive layers that are electrically connected to a plurality of memory cells arranged in a first direction on a semiconductor substrate, the first direction intersecting a surface of the semiconductor substrate;

a stepped part for contacting the plurality of conductive layers to a wiring line;

a contact extending in the first direction and being connected to the conductive layer in the stepped part; and

a plurality of columnar bodies extending in the first direction and penetrates the conductive layer in the stepped part and including a first columnar body having a first height and a second columnar body having a second height which is lower than the first height.

2. The semiconductor memory device according to claim 1, wherein

the stepped part up to the second height has the second columnar body provided therein, and the stepped part above the second height has the first columnar body provided therein.

3. The semiconductor memory device according to claim 1, wherein

the second height is not less than half of the first height.

4. The semiconductor memory device according to claim 1, wherein

the stepped part is disposed on each of both sides sandwiching the memory cell array region.

5. The semiconductor memory device according to claim 1, wherein

the columnar body is composed of materials including oxygen and silicon.

6. The semiconductor memory device according to claim 1, wherein

the first columnar body and the second columnar body are composed of different materials.

7. The semiconductor memory device according to claim 1, wherein

each of the plurality of memory cells includes a semiconductor layer extending in the first direction and a memory film provided on a side surface of the semiconductor layer, and

the first columnar body includes the semiconductor layer and the memory film.

8. The semiconductor memory device according to claim 1, wherein

a distance between extremities of the conductive layers adjacent in the first direction up to the conductive layer having the second height is shorter than that of the conductive layers adjacent in the first direction above the second height.

9. The semiconductor memory device according to claim 1, wherein

the plurality of conductive layers configuring the stepped part each include a projecting part whose end projects more than an end of the conductive layer adjacent upwardly in the first direction, and

the contact and the columnar body are provided in an identical one of the projecting parts.

10. The semiconductor memory device according to claim 9, wherein

a distance between the first columnar body and the contact provided in one of the projecting parts is shorter than a distance between the second columnar body and the contact provided in another one of the projecting parts.

11. A method of manufacturing a semiconductor memory device, the semiconductor memory device comprising:

a memory cell array region, the memory cell array region including a plurality of conductive layers that are electrically connected to a plurality of memory cells arranged in a first direction on a semiconductor substrate, the first direction intersecting a surface of the semiconductor substrate;

a stepped part for contacting the plurality of conductive layers to a wiring line;

a contact connected to the conductive layer in the stepped part; and

a columnar body that extends in the first direction and penetrates the conductive layer in the stepped part,

a plurality of the columnar bodies being provided, and

the plurality of columnar bodies including a first columnar body and a second columnar body, the first columnar body having a first height, and the second columnar body having a second height which is lower than the first height,

the method of manufacturing comprising;

alternately stacking a plurality of insulating layers and first layers on the semiconductor substrate;

forming ends of the insulating layer and the first layer in a stepped shape, thereby forming a first stepped part;

forming a first hole that penetrates the plurality of insulating layers and first layers, the first hole being formed close to an extremity of one of steps configuring the first stepped part;

forming a second layer in the first hole to form the second columnar body;

alternately stacking a plurality of the insulating layers and the first layers on the first stepped part;

forming in a stepped shape ends of a plurality of the insulating layers and first layers stacked on the first stepped part, thereby forming a second stepped part;

forming a second hole that penetrates the plurality of insulating layers and first layers, the second hole being formed close to an extremity of one of steps configuring the second stepped part;

forming a third layer in the second hole to form the first columnar body;

forming a third hole closely adjacent to the first columnar body and the second columnar body; and

forming a conductive film in the third hole to form the contact.

12. The method of manufacturing a semiconductor memory device according to claim 11, further comprising

making a distance between extremities of each layer of the first stepped part when forming the first stepped part shorter than that of each layer of the second stepped part when forming the second stepped part.

13. The method of manufacturing a semiconductor memory device according to claim 11, further comprising

making a number of layers included in the first stepped part more numerous than that of layers included in the second stepped part.

14. The method of manufacturing a semiconductor memory device according to claim 11, wherein

the plurality of memory cells each include:

a semiconductor layer extending in the first direction and a memory film provided on a side surface of the semiconductor layer, and

the method of manufacturing further comprises;

when forming the first hole, forming a first memory hole in the memory cell array region;

forming the second layer in the first memory hole;

when forming the second hole, forming a second memory hole on the second layer;

removing the second layer in the first memory hole via the second memory hole, thereby forming a third memory hole having the first and second memory holes communicated with each other; and

forming the semiconductor layer and the memory film in the third memory hole, thereby forming the plurality of memory cells.

15. The method of manufacturing a semiconductor memory device according to claim 14, wherein

the third layer formed in the second hole includes the semiconductor layer and the memory film, and

forming the third layer in the second hole is performed simultaneously to forming the semiconductor layer and the memory film in the third memory hole.