SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• US 20170278931A1
• Filed: 02/28/2017
• Published: 09/28/2017
• Est. Priority Date: 03/22/2016
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: IGUCHI, Kenichi, NAKAZAWA, Haruo
• Granted Patent: US 10,559,664 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0485 Ohmic electrodes
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03848 Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/29101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/32112 : the layer connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/00 : Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 29/1608 : Silicon carbide
• CPC Class Codes: H01L 29/45 : Ohmic electrodes
• CPC Class Codes: H01L 29/66068 : the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10158 : at the passive surface

Abstract

A method of manufacturing a semiconductor device includes assigning a plurality of chip regions on an epitaxial-growth layer of a semiconductor substrate where the epitaxial-growth layer is grown on a bulk layer and forming a plurality of device structures on the plurality of chip regions, respectively, thinning the semiconductor substrate from a bottom-surface side of the bulk layer, bonding a supporting-substrate on a bottom surface of the thinned semiconductor substrate, selectively removing the supporting-substrate so that the bottom surface of the semiconductor substrate is exposed, at locations corresponding to positions of each of main current paths in the plurality of device structures, respectively, dicing the semiconductor substrate together with the supporting-substrate along dicing lanes between the plurality of the chip regions so as to form a plurality of chips.

Claims

1. A method of manufacturing a semiconductor device including:

assigning a plurality of chip regions on an epitaxial-growth layer of a semiconductor substrate where the epitaxial-growth layer is grown on a bulk layer and forming a plurality of device structures on the plurality of chip regions, respectively;

thinning the semiconductor substrate from a bottom-surface side of the bulk layer;

bonding a supporting-substrate on a bottom surface of the thinned semiconductor substrate;

selectively removing the supporting-substrate so that the bottom surface of the semiconductor substrate is exposed, at locations corresponding to positions of each of main current paths in the plurality of device structures, respectively; and

dicing the semiconductor substrate together with the supporting-substrate along dicing lanes between the plurality of the chip regions so as to form a plurality of chips.

2. The method of claim 1, wherein a material of the semiconductor substrate is a wide bandgap semiconductor material.

3. The method of claim 2, wherein the material of the semiconductor substrate is silicon carbide.

4. The method of claim 1, wherein a material of the supporting-substrate is a semiconductor material different from that of the semiconductor substrate.

5. The method of claim 4, wherein the supporting-substrate is a single crystalline silicon substrate.

6. The method of claim 1, wherein the selectively removing the supporting-substrate is executed so that the bottom surface of the epitaxial-growth layer is exposed.

7. The method of claim 1, wherein the selectively removing the supporting-substrate is executed by anisotropic etching.

8. The method of claim 1, further including forming a bottom-surface electrode by forming an ohmic contact layer on the bottom-surface side of the semiconductor substrate and forming a silicide of the ohmic contact layer.

9. The method of claim 8, wherein the forming an ohmic contact layer is performed at a temperature of 500°

C. or more and a melting point of silicon or less.

10. The method of claim 8, wherein the ohmic contact layer comprises at least one of nickel, titanium, aluminum, molybdenum, and chromium.

11. The method of claim 1, wherein a material used in the forming a plurality of the device structures has a melting point being higher than any one of the highest temperatures reachable in the bonding a supporting-substrate and the selectively removing the supporting-substrate.

12. The method of claim 1, wherein the bonding a supporting-substrate is performed by activating a bonding surface of the semiconductor substrate and the supporting-substrate.

13. The method of claim 12, wherein the activating a bonding surface is performed by plasma, gas, or beam.

14. The method of claim 1, wherein the bonding a supporting-substrate is a direct bonding of the semiconductor substrate and the supporting-substrate.

15. The method of claim 1, wherein the bonding is performed by forming an intermediate layer on a bonding surface of at least one of the semiconductor substrate and the supporting-substrate and bonding the semiconductor substrate and the supporting-substrate through the intermediate layer.

16. The method of claim 15, wherein the intermediate layer is a layer containing water molecules having a thickness at molecular layer level.

17. The method of claim 1, wherein an active area including the device structures is arranged in the inside of the supporting leg.

18. The method of claim 17, wherein a breakdown-voltage improving-structure is provided around the active area.

19. A semiconductor device comprising:

a semiconductor layer having a stacked structure including an epitaxial-growth layer;

a device structure provided on the epitaxial-growth layer;

a supporting leg made of a semiconductor different from that of the semiconductor layer and selectively provided on a bottom surface of the semiconductor layer so that a bottom surface corresponding to a position of a main current path of the device structure is exposed; and

a bottom-surface electrode as an ohmic contact provided on the exposed bottom-surface side of the semiconductor layer.

20. A semiconductor device comprising:

an epitaxial-growth layer of a semiconductor;

a device structure provided on the epitaxial-growth layer;

a supporting leg selectively provided on a bottom surface of the epitaxial-growth layer so that a bottom surface corresponding to a position of a main current path of the device structure is exposed; and

a bottom-surface electrode as an ohmic contact provided on the exposed bottom-surface side of the epitaxial-growth layer.