PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

• US 20170280560A1
• Filed: 03/21/2017
• Published: 09/28/2017
• Est. Priority Date: 03/22/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, Soo-jae
• Granted Patent: US 10,448,508 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/16503 comprising an intermetallic compound
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/00 Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/35 : Mechanical effects
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/094 : Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
• CPC Class Codes: H05K 2201/09745 : Recess in conductor, e.g. in pad or in metallic substrate
• CPC Class Codes: H05K 2201/098 : Special shape of the cross-section of conductors, e.g. very thick plated conductors
• CPC Class Codes: H05K 2201/09845 : Stepped hole, via, edge, bump or conductor
• CPC Class Codes: H05K 2201/099 : Coating over pads, e.g. solder resist partly over pads
• CPC Class Codes: H05K 2201/10378 : Interposers
• CPC Class Codes: H05K 2201/10674 : Flip chip

Abstract

A printed circuit board (PCB) having a reliable electrical connection with connection terminals and a semiconductor package including the PCB, the printed circuit board including: a substrate base; a plurality of pads disposed on upper and lower surfaces of the substrate base; and a solder resist layer configured to cover at least a portion of the upper and lower surfaces of the substrate base, wherein at least some of the plurality of pads are groove pads comprising at least one annular groove in a side opposite to the substrate base.

Claims

1. A printed circuit board (PCB) comprising:

a substrate base;

a plurality of pads on upper and lower surfaces of the substrate base; and

a solder resist layer covering at least a portion of the upper and lower surfaces of the substrate base,

wherein at least some of the plurality of pads are groove pads comprising at least one annular groove in a side opposite to the substrate base.

2. The PCB of claim 1, wherein the solder resist layer fills at least a portion of the at least one annular groove.

3. The PCB of claim 1, wherein the solder resist layer covers a portion of at least one of the plurality of pads and defines a connection terminal contact region therein.

4. The PCB of claim 3, wherein the at least one annular groove of at least one of the groove pads is spaced apart from the connection terminal contact region.

5. The PCB of claim 1, wherein at least some of the groove pads comprise at least two annular grooves spaced apart from each other.

6. The PCB of claim 5, wherein the at least two annular grooves spaced apart from each other have substantially the same depth.

7. The PCB of claim 1, wherein at least some of the groove pads comprise at least two annular grooves connected to each other.

8. The PCB of claim 7, wherein the at least two annular grooves connected to each other have different depths.

9. The PCB of claim 1, wherein some of the plurality of pads are groove pads, and others of the plurality of pads are planar pads,

wherein the planar pads are disposed closer to a center of the substrate base from a perimeter of the substrate base relative to the groove pads.

10. The PCB of claim 1, wherein the groove pads comprise a first groove pad including one annular groove and a second groove pad including two annular grooves,

wherein the first groove pad is disposed closer to a center of the substrate base from a perimeter of the substrate base relative to the second groove pad.

11. A semiconductor package comprising:

a printed circuit board (PCB) comprising a substrate base, a plurality of pads on upper and lower surfaces of the substrate base, and a solder resist layer covering at least a portion of the lower surface of the substrate base;

a semiconductor chip electrically connected to the plurality of pads on the upper surface of the substrate base; and

a plurality of connection terminals attached to the plurality of pads on the lower surface of the substrate base,

wherein at least some of the plurality of pads are groove pads comprising at least one annular groove in a side opposite to the substrate base.

12. The semiconductor package of claim 11, wherein at least some of the plurality of pads on the lower surface of the substrate base are the groove pads.

13. The semiconductor package of claim 12, wherein the solder resist layer covers some of the groove pads, fills the at least one annular groove, and defines a connection terminal contact region in the groove pads.

14. The semiconductor package of claim 13, wherein at least one of the plurality of connection terminals attached to the groove pads is spaced apart from the at least one annular groove with the solder resist layer therebetween.

15. The semiconductor package of claim 11, wherein at least some of the groove pads comprise at least two annular grooves spaced apart from each other and having substantially the same depth.

16. A device comprising:

a substrate base;

a plurality of pads on upper and lower surfaces of the substrate base; and

a solder resist layer covering a portion of the upper and lower surfaces of the substrate base,

wherein each pad comprises a first side and a second side, wherein the first side is arranged adjacent to the substrate base and wherein the second side is arranged opposite to the first side,

wherein at least some of the plurality of pads are groove pads comprising at least one groove formed in the second side of the groove pads;

wherein the solder resist layer defines a connection terminal contact region in the groove pads, and wherein the at least one groove substantially surrounds the connection terminal contact region.

17. The device of claim 16, further comprising a plurality of connection terminals attached to corresponding ones of the groove pads to form a contact surface between the plurality of connection terminals and the corresponding ones of the groove pads,

wherein the at least one groove substantially surrounds the contact surface between the plurality of connection terminals and the corresponding ones of the groove pads.

18. The device of claim 16, wherein the grooves comprise an annular groove.

19. The device of claim 18, wherein the annular groove extends inwardly from a side surface of a corresponding one of the groove pads.

20. The device of claim 17, wherein the grooves comprise a first annular groove and a second annular groove connected to each other, and wherein the second annular groove extends inwardly from a side surface of one of the groove pads, and wherein an inner edge of the second annular groove has a circular shape in plan view and an outer edge thereof has the same shape as that of a perimeter of the groove pad.