CAPACITIVE SENSING DEVICE WITH SINGLE REFERENCE CHANNEL

• US 20170285833A1
• Filed: 03/30/2016
• Published: 10/05/2017
• Est. Priority Date: 03/30/2016
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: SHAHROKHI, Farzaneh, SCHWARTZ, Adam L.
• Granted Patent: US 10,365,749 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/041662 using alternate mutual and self-capacitive scanning
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

An example a processing system for a capacitive sensing device includes a reference transmitter coupled to a reference capacitance. The processing system further includes a charge accumulation circuit having an input coupled to the reference transmitter through the reference capacitance and configured to generate an integrated signal, a demodulator circuit having an input coupled to an output of the charge accumulation circuit and configured to demodulate the integrated signal to generate at least one demodulated signal, a sampling circuit having an input coupled to an output of the demodulator circuit and configured to sample the demodulated signal(s), a first reference buffer coupled to an output of the sampling circuit, the first reference buffer outputting a first voltage reference for the capacitive sensing device, and a second reference buffer coupled to the output of the sampling circuit, the second reference buffer outputting a second voltage reference for the capacitive sensing device.

Claims

1. A processing system for a capacitive sensing device, comprising:

a reference transmitter coupled to a reference capacitance;

a charge accumulation circuit having an input coupled to the reference transmitter through the reference capacitance and configured to generate an integrated signal;

a demodulator circuit having an input coupled to an output of the charge accumulation circuit and configured to demodulate the integrated signal to generate at least one demodulated signal;

a sampling circuit having an input coupled to an output of the demodulator circuit and configured to sample the at least one demodulated signal;

a first reference buffer coupled to an output of the sampling circuit, the first reference buffer outputting a first voltage reference for the capacitive sensing device; and

a second reference buffer coupled to the output of the sampling circuit, the second reference buffer outputting a second voltage reference for the capacitive sensing device.

2. The processing system of claim 1, wherein each of the first reference buffer and the second reference buffer are coupled through the demodulator circuit to the same components of the reference transmitter and the charge accumulation circuit.

3. The processing system of claim 1, wherein the demodulator circuit comprises:

a first demodulator and a second demodulator each comprising a detector coupled to a low-pass filter, which is in turn coupled to an amplifier;

wherein an input of the detector in each of the first demodulator and the second demodulator is coupled to the output of the charge accumulation circuit; and

wherein an output of the amplifier in each of the first demodulator and the second demodulator is coupled to the input of the sampling circuit.

4. The processing system of claim 3, wherein a polarity of the detector in the first demodulator is opposite a polarity of the detector in the second demodulator.

5. The processing system of claim 1, wherein the demodulator circuit comprises:

a single demodulator comprising a detector coupled to a low-pass filter, which is in turn coupled to an amplifier;

wherein an input of the detector is coupled to the output of the charge accumulation circuit; and

wherein an output of the amplifier is coupled to the input of the sampling circuit.

6. The processing system of claim 1, wherein the sampling circuit comprises a first sample-and-hold circuit and a second sample-and-hold circuit.

7. The processing system of claim 6, wherein each of the first sample-and-hold circuit and the second sample-and-hold circuit is configured to sample and hold with respect to an intermediate voltage reference between a ground voltage and a supply voltage.

8. The processing system of claim 6, wherein the first sample-and-hold circuit is configured to sample and hold with respect to a ground voltage, and wherein the second sample-and-hold circuit is configured to sample with respect to the ground voltage and hold with respect to a supply voltage.

9. An input device, comprising:

a plurality of sensor electrodes; and

a processing system, coupled to the plurality of sensor electrodes, including a plurality of sensor channels coupled to the plurality of sensor electrodes and a single reference channel coupled to a reference transmitter through a reference capacitance, the reference channel comprising;

a charge accumulation circuit having an input coupled to the reference transmitter through the reference capacitance and configured to generate an integrated signal;

a demodulator circuit having an input coupled to an output of the charge accumulation circuit and configured to demodulate the integrated signal to generate at least one demodulated signal;

a sampling circuit having an input coupled to an output of the demodulator circuit and configured to sample the at least one demodulated signal;

a first reference buffer coupled to an output of the sampling circuit, the first reference buffer outputting a first voltage reference for the capacitive sensing device; and

a second reference buffer coupled to the output of the sampling circuit, the second reference buffer outputting a second voltage reference for the capacitive sensing device.

10. The input device of claim 9, wherein each of the first reference buffer and the second reference buffer are coupled through the demodulator circuit to the same components of the reference transmitter and the charge accumulation circuit.

11. The input device of claim 9, wherein the demodulator circuit comprises:

a first demodulator and a second demodulator each comprising a detector coupled to a low-pass filter, which is in turn coupled to an amplifier;

wherein an input of the detector in each of the first demodulator and the second demodulator is coupled to the output of the charge accumulation circuit; and

wherein an output of the amplifier in each of the first demodulator and the second demodulator is coupled to the input of the sampling circuit.

12. The input device of claim 11, wherein a polarity of the detector in the first demodulator is opposite a polarity of the detector in the second demodulator.

13. The input device of claim 9, wherein the demodulator circuit comprises:

a single demodulator comprising a detector coupled to a low-pass filter, which is in turn coupled to an amplifier;

wherein an input of the detector is coupled to the output of the charge accumulation circuit; and

wherein an output of the amplifier is coupled to the input of the sampling circuit.

14. The input device of claim 9, wherein the sampling circuit comprises a first sample-and-hold circuit and a second sample-and-hold circuit.

15. The input device of claim 14, wherein each of the first sample-and-hold circuit and the second sample-and-hold circuit is configured to sample and hold with respect to an intermediate voltage reference between a ground voltage and a supply voltage.

16. The input device of claim 14, wherein the first sample-and-hold circuit is configured to sample and hold with respect to a ground voltage, and wherein the second sample-and-hold circuit is configured to sample with respect to the ground voltage and hold with respect to a supply voltage.

17. A method of generating reference voltages for a capacitive sensing device, comprising:

coupling a transmitter signal to a reference capacitance;

integrating output of the reference capacitance to generate an integrated signal;

demodulating the integrated signal to generate at least one demodulated signal;

sampling the at least one demodulated signal; and

buffering the sampled at least one demodulated signal to output a first voltage reference and a second voltage reference.

18. The method of claim 17, wherein the step of demodulating comprises:

demodulating, filtering, and amplifying the integrated signal to generate a first demodulated signal comprising a high reference voltage; and

demodulating, filtering, and amplifying the integrated signal to generate a second demodulated signal comprising a low reference voltage.

19. The method of claim 17, wherein the step of demodulating comprises demodulating, filtering, and amplifying the integrated signal to generate a single demodulated signal, and wherein the step of sampling comprises sampling the demodulated signal to generate high and low reference voltages.

20. The method of claim 17, further comprising:

coupling the first voltage reference and the second voltage reference to an analog-to-digital converter (ADC) in each of a plurality of sensor channels in the capacitive sensing device.