READ DELIVERY FOR MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL

• US 20170285941A1
• Filed: 04/01/2016
• Published: 10/05/2017
• Est. Priority Date: 04/01/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: NALE, Bill, VOGT, Pete D.
• Granted Patent: US 10,339,072 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4018 with data-width conversion
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A system includes a repeater architecture for reads where memory connects to a host for with one bandwidth, and repeats the channel with a lower bandwidth. A memory circuit includes a first group of read signal lines to couple point-to-point between a first group of memory devices and a host device. The memory circuit includes a second, smaller group of read signal lines to couple point-to-point between the first group of memory devices and a second group of memory devices, to extend the memory channel to the second group of memory devices. The memory circuit includes a repeater to share read bandwidth between the first and second groups of memory devices, with up to a portion of the bandwidth for reads to the second group of memory devices, and at least an amount equal to the bandwidth less the portion for reads to the first group of memory devices.

Claims

1. A memory circuit, comprising:

a first group of memory devices coupled to a first memory channel, the first memory channel with a first bandwidth to send read data to a host device;

a second group of memory devices coupled to a second memory channel, the second memory channel coupled to the first memory channel and with a second bandwidth to send read data to the host device, the second bandwidth a portion of the first bandwidth; and

a repeater to couple the second memory channel to the first memory channel, the repeater to share the first bandwidth between the first and second groups of memory devices, wherein the repeater is to provide access to up to the portion of the first bandwidth to send read data to the host, and to provide access to at least an amount equal to the first bandwidth less the portion to the first group of memory devices to send read data to the host.

2. The memory circuit of claim 1, wherein the portion comprises half.

3. The memory circuit of claim 2, wherein the repeater is to share the first bandwidth between the first and second groups of memory devices, including to allocate half of read address signal lines of the first memory channel to the first group of memory devices, and to allocate another half of read address signal lines of the first memory channel to passthrough read data from the second memory channel to the host device.

4. The memory circuit of claim 3, further comprising a multiplexer to select between a coupling of the other half of read address signal lines of the first memory channel to the second memory channel, and a coupling of the other half of read address signal lines of the first memory channel to the first group of memory devices.

5. The memory circuit of claim 1, wherein the repeater is to share the first bandwidth between the first and second groups of memory devices, including to accumulate read data from the second group of memory devices with the second bandwidth, and burst the accumulated read data to the host device with the first bandwidth.

6. The memory circuit of claim 5, wherein the repeater is to begin to burst the accumulated read data after accumulation of half of read data cycles for a read operation from the second group of memory devices.

7. The memory circuit of claim 5, wherein the second group of memory devices is to first send a critical chunk of read data, and the repeater is to begin to burst the accumulated read data after accumulation of the critical chunk of read data.

8. The memory circuit of claim 1, wherein the repeater is to share the first bandwidth between the first and second groups of memory devices, including to provide access to the first bandwidth to the first group of memory devices whenever the second group of memory devices has no read data to send to the host device, and to accumulate and burst read data from the second group of memory devices to the host device with the first bandwidth when the second group of memory devices has data to send to the host device.

9. The memory circuit of claim 8, wherein the repeater is to limit access to the second group of memory devices to selected, non-consecutive read operations, and is to provide access to the first group of memory devices to consecutive read operations.

10. The memory circuit of claim 1, wherein the first group of memory devices comprises memory devices of a first memory module, and the second group of memory devices comprises memory devices of a second memory module.

11. The memory circuit of claim 10, wherein the first memory module comprises a dual inline memory module (DIMM) including synchronous dynamic random access memory (SDRAM) devices compliant with a dual data rate version 5 (DDR5) standard, and the second memory module comprises a DIMM including SDRAM devices compliant with a dual data rate version 5 (DDR5) standard.

12. The memory circuit of claim 10, wherein the first memory module comprises a dual inline memory module (DIMM) including synchronous dynamic random access memory (SDRAM) devices compliant with a dual data rate version 5 (DDR5) standard, and the second memory module comprises a DIMM including byte-addressable, random access nonvolatile memory devices.

13. The memory circuit of claim 12, wherein the byte-addressable, random access nonvolatile memory devices comprise three dimensional memory devices including memory cells with chalcogenide glass.

25. The memory system of claim 13, wherein the first memory module comprises a dual inline memory module (DIMM) including synchronous dynamic random access memory (SDRAM) devices compliant with a dual data rate version 5 (DDR5) standard, and the second memory module comprises a DIMM including byte-addressable, random access nonvolatile memory devices.

14. A memory system, comprising:

a memory controller circuit to control access to memory;

a first memory module to couple to the memory controller circuit via a primary segment of a memory channel, the first memory module including multiple dynamic random access memory (DRAM) devices and a repeater, and the primary segment of the memory channel with a bandwidth to send read data to the memory controller circuit; and

a second memory module to couple to the memory controller circuit through the repeater via a secondary segment of the memory channel, the second memory module including multiple DRAM devices, and the secondary segment of the memory channel with a portion of the bandwidth to send read data to the memory controller circuit, the portion less than the bandwidth;

wherein the repeater is to provide access to up to the portion of the bandwidth to the second memory module, and to provide access to at least an amount equal to the bandwidth less the portion to the first memory module.

15. The memory system of claim 14, wherein the portion comprises half.

16. The memory system of claim 15, wherein the repeater is to share the first bandwidth between the first and second groups of memory devices, including to allocate half of read address signal lines of the primary segment to the first group of memory devices, and to allocate another half of read address signal lines of the primary segment to passthrough read data from the secondary segment to the host device.

17. The memory system of claim 16, further comprising a multiplexer to select between a coupling of the other half of read address signal lines of the primary segment to the secondary segment, and a coupling of the other half of read address signal lines of the primary segment to the first group of memory devices.

18. The memory system of claim 15, wherein the repeater is to share the first bandwidth between the first and second groups of memory devices, including to accumulate read data from the second group of memory devices with the second bandwidth, and burst the accumulated read data to the host device with the first bandwidth.

19. The memory system of claim 18, wherein the repeater is to begin to burst the accumulated read data after accumulation of half of read data cycles for a read operation from the second group of memory devices.

20. The memory system of claim 18, wherein the second group of memory devices is to first send a critical chunk of read data, and the repeater is to begin to burst the accumulated read data after accumulation of the critical chunk of read data.

21. The memory system of claim 14, wherein the repeater is to share the first bandwidth between the first and second groups of memory devices, including to provide access to the first bandwidth to the first group of memory devices whenever the second group of memory devices has no read data to send to the host device, and to accumulate and burst read data from the second group of memory devices to the host device with the first bandwidth when the second group of memory devices has data to send to the host device.

22. The memory system of claim 21, wherein the repeater is to limit access to the second group of memory devices to selected read operations, and is to provide access to the first group of memory devices to consecutive read operations.

23. The memory system of claim 14, wherein the memory channel comprises a first memory channel, and further comprising the first memory module to couple to the memory controller circuit via a primary segment of the first memory channel and to couple to the memory controller circuit via a primary segment of a second memory channel, and the second memory module to couple to a secondary segment of the first memory channel and to a secondary segment of the second memory channel.

24. The memory system of claim 14, wherein the first memory module comprises a dual inline memory module (DIMM) including synchronous dynamic random access memory (SDRAM) devices compliant with a dual data rate version 5 (DDR5) standard, and the second memory module comprises a DIMM including SDRAM devices compliant with a dual data rate version 5 (DDR5) standard.

26. The memory system of claim 14, further comprising one or more of

a multicore processor coupled to the memory controller, at least one core of the processor to execute data stored in the memory modules;

a network adapter coupled to exchange data between the memory modules and a remote network location;

a display communicatively coupled to the processor;

a battery to provide power to the memory system.