SYSTEMS AND METHODS FOR OFFLOADING PROCESSING FROM A HOST TO STORAGE PROCESSING UNITS USING AN INTERCONNECT NETWORK

• US 20170286170A1
• Filed: 03/29/2016
• Published: 10/05/2017
• Est. Priority Date: 03/29/2016
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: HGST Netherlands B.V. (Western Digital Corporation)
• Inventors: De, Arup, Gunnam, Kiran Kumar
• Granted Patent: US 10,095,445 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 9/5033 considering data affinity

Abstract

Systems and methods for offloading processing from a host to one or more storage processing units using an interconnect network are provided. One such system includes a host having a processing task, a plurality of storage processing units (SPUs), a host interface configured to enable communications between the host and each of the plurality of SPUs, and an interconnection network coupled to at least two of the plurality of SPUs, where the host is configured to command at least one of the plurality of SPUs to perform the processing task, and command the interconnection network to couple two or more of the plurality of SPUs.

Claims

1. A system for offloading processing from a host to one or more storage processing units each comprising a non-volatile memory (NVM), the system comprising:

a host having a processing task;

a plurality of storage processing units (SPUs);

a host interface configured to enable communications between the host and each of the plurality of SPUs; and

an interconnection network coupled to at least two of the plurality of SPUs;

wherein the host is configured to;

command at least one of the plurality of SPUs to perform the processing task; and

command the interconnection network to couple two or more of the plurality of SPUs.

2. The system of claim 1, wherein each of the plurality of SPUs is configured to perform local processing.

3. The system of claim 1, wherein each of the plurality of SPUs comprise an NVM and a processing circuitry configured to perform the processing task.

4. The system of claim 1, wherein a first SPU of the coupled two or more of the plurality of SPUs is configured to communicate with a second SPU of the coupled two or more of the plurality of SPUs using the interconnection network.

5. The system of claim 4, wherein the first SPU is configured to communicate with the second SPU using the interconnection network instead of the host interface.

6. The system of claim 4, wherein the first SPU is configured to send data to the second SPU using the interconnection network.

7. The system of claim 1, wherein the interconnection network is coupled to all of the plurality of SPUs.

8. The system of claim 1, wherein the interconnection network is configured to enable direct data transfer between SPUs connected thereto.

9. The system of claim 1, wherein the host interface and the interconnection network are distinct networks.

10. The system of claim 1, wherein the host interface comprises a Peripheral Component Interconnect Express (PCIe) network.

11. The system of claim 1, wherein the interconnection network comprises at least one of an Omega network, a Butterfly network, a crossbar switch network, or a Benes network.

12. A method for offloading processing from a host to one or more storage processing units each comprising a non-volatile memory (NVM), the method comprising:

sending a processing task from the host to a first storage processing unit (SPU) of a plurality of SPUs via a host interface;

commanding the first SPU to perform the processing task; and

commanding an interconnection network to couple two or more of the plurality of SPUs, wherein the interconnection network is configured to enable direct data transfer between SPUs connected thereto.

13. The method of claim 12, wherein the first SPU is configured to perform local processing.

14. The method of claim 12, wherein the first SPU is configured to communicate with a second SPU of the coupled two or more of the plurality of SPUs using the interconnection network.

15. The method of claim 14, wherein the first SPU is configured to communicate with the second SPU using the interconnection network instead of the host interface.

16. The method of claim 12, wherein the interconnection network is coupled to all of the plurality of SPUs.

17. The method of claim 12, wherein the interconnection network comprises at least one of an Omega network, a Butterfly network, a crossbar switch network, or a Benes network.

18. A method for offloading processing from a host to one or more storage processing units each comprising a non-volatile memory (NVM), the method comprising:

receiving a processing task from the host at a first storage processing unit (SPU) of a plurality of SPUs via a host interface;

performing, at the first SPU, the processing task; and

transferring data from the first SPU to a second SPU via an interconnection network.

19. The method of claim 18, wherein each of the plurality of SPUs comprises an NVM and a processing circuitry configured to perform the processing task.

20. The method of claim 18, wherein the performing, at the first SPU, the processing task comprises:

generating data as a result of the performing the processing task; and

the transferring the data to the second SPU via the interconnection network.

21. The method of claim 18, further comprising communicating with the second SPU using the interconnection network instead of the host interface.

22. The method of claim 18, wherein the host interface and the interconnection network are distinct networks.

23. The method of claim 18, wherein the interconnection network comprises at least one of an Omega network, a Butterfly network, a crossbar switch network, or a Benes network.

24. A method for offloading processing from a host to one or more storage processing units each comprising a non-volatile memory (NVM), the method comprising:

receiving a processing task from the host at a second storage processing unit (SPU) of a plurality of SPUs via a host interface;

performing, at the second SPU, the processing task; and

receiving data, at the second SPU, from a first SPU via an interconnection network.

25. The method of claim 24, wherein each of the plurality of SPUs comprises an NVM and a processing circuitry configured to perform the processing task.

26. The method of claim 24, wherein the performing, at the second SPU, the processing task comprises:

generating data at the second SPU as a result of the performing the processing task;

the receiving, at the second SPU, the data from the first SPU via the interconnection network; and

storing, at the second SPU, the data generated at the second SPU and the data received from the first SPU.

27. The method of claim 24, further comprising communicating with the first SPU using the interconnection network instead of the host interface.

28. The method of claim 24, wherein the host interface and the interconnection network are distinct networks.

29. The method of claim 24, wherein the interconnection network comprises at least one of an Omega network, a Butterfly network, a crossbar switch network, or a Benes network.