MEMORY DEVICES INCLUDING DYNAMIC SUPERBLOCKS, AND RELATED METHODS AND ELECTRONIC SYSTEMS

• US 20170286286A1
• Filed: 03/29/2016
• Published: 10/05/2017
• Est. Priority Date: 03/29/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Szubbocsev, Zoltan
• Granted Patent: US 10,540,274 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A memory device includes a memory array having non-volatile memory cells, and a memory controller configured to dynamically construct a superblock during each garbage collection process based, at least in part, on an amount of valid data present in each physical block of the memory array. Another memory device includes physical blocks of memory cells and a memory controller configured to construct a new superblock dynamically each time garbage collection occurs for the physical blocks regardless of whether any physical blocks are determined to be bad. Additional methods for managing operation of a memory device and related electronic systems are also described.

Claims

1. A memory device, comprising:

a memory array having non-volatile memory cells; and

a memory controller operably coupled to the memory array, the memory controller configured to dynamically construct a superblock for at least one garbage collection process based, at least in part, on an amount of valid data present in each physical block of the memory array.

2. The memory device of claim 1, wherein the memory controller includes a flash translation layer configured to perform the garbage collection and address mapping for the memory controller.

3. The memory device of claim 1, wherein the memory array includes dies having different physical blocks of data.

4. The memory device of claim 3, wherein the dies include:

a first die and a second die managed by a first channel of the memory controller; and

a third die and a fourth die managed by a second channel of the memory controller.

5. The memory device of claim 4, wherein the memory controller is configured to construct the superblock by selecting a physical block from either the first die or the second die that has a lowest amount of valid data for the first channel, and selecting another physical block from either the third die or the fourth die that has a lowest amount of valid data for the second channel.

6. The memory device of claim 4, wherein the memory controller is configured to construct the superblock by selecting multiple physical blocks one or more of the first die or the second die, and selecting multiple physical blocks from one or more of the third die or the fourth die.

7. The memory device of claim 1, wherein the memory controller is further configured to dynamically determine a size for the superblock for the at least one garbage collection process based, at least in part, on a number of physical blocks needed to be cleared during a given garbage collection process.

8. The memory device of claim 7, wherein the memory controller is configured to construct a first superblock according to a first set of rules during a first garbage collection process, and a second superblock according to a second set of rules during a second garbage collection process.

9. The memory device of claim 1, wherein the non-volatile memory cells of the memory array are configured as at least one of NAND Flash, NOR Flash, erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), ferroelectric RAM (FRAM), or magnetoresistive RAM (MRAM).

10. A memory device, comprising:

physical blocks of memory cells; and

a memory controller configured to construct a new superblock dynamically each time garbage collection occurs for the physical blocks regardless of whether any physical blocks are determined to be bad.

11. The memory device of claim 10, wherein the memory controller is configured to execute firmware having an application layer, a file system layer, and a translation layer.

12. The memory device of claim 11, wherein the translation layer includes a Flash Translation Layer (FTL) configured to construct the new superblock and perform the garbage collection.

13. The memory device of claim 12, wherein the FTL is configured to construct the new superblock responsive to determining a set of physical blocks having a minimum total amount of valid data.

14. The memory device of claim 13, wherein the set of physical blocks includes at least one physical block from a die that is part of a channel managed by the memory controller, and at least one additional physical block from an additional die that is part of another channel managed by the memory controller.

15. The memory device of claim 13, wherein the set of physical blocks includes physical blocks from different dies that comprise the memory cells.

16. The memory device of claim 13, wherein the set of physical blocks includes physical blocks from a common die that comprise the memory cells.

17. A method for managing operation of a memory device, the method comprising:

initiating a garbage collection process for a memory array divided into physical blocks of data;

determining an amount of valid data for the physical blocks of data; and

constructing a dynamic superblock based, at least in part, on the amount of valid data for the physical blocks of data for the memory array.

18. The method of claim 17, further comprising:

moving valid data for physical blocks selected for construction of the dynamic superblock; and

erasing the physical blocks selected for construction of the dynamic superblock.

19. The method of claim 17, wherein initiating the garbage collection process includes:

separating and recovering valid data from invalid data for the physical blocks of the dynamic superblock;

re-distributing the valid data into a pool of available physical blocks outside of the dynamic superblock; and

erasing the physical blocks of the dynamic superblock to free up space therein for additional writes to occur.

20. The method of claim 17, wherein determining the amount of valid data for the physical blocks of data includes:

searching through physical blocks for each die managed by a first channel to determine valid data for each physical block of the first channel; and

searching through physical blocks for each die managed by a second channel to determine valid data for each physical block of the second channel.

21. The method of claim 20, wherein constructing the dynamic superblock includes linking at least one physical block for the first channel with at least one physical block for the second channel.

22. The method of claim 21, wherein linking at least one physical block for the first channel with at least one physical block for the second channel includes:

selecting the at least one physical block for the first channel having a minimum amount of valid data among the physical blocks for the first channel; and

selecting the at least one physical block for the second channel having a minimum amount of valid data among the physical blocks for the second channel.

23. An electronic system, comprising:

a memory device including dies having physical blocks, the memory device configured to link a first set of physical blocks to dynamically construct a first superblock responsive to a first garbage collection process, and link a second set of physical blocks to dynamically construct a second superblock responsive to a second garbage collection process.

24. The electronic system of claim 23, further comprising at least one of an embedded multi-media controller (eMMC), a Solid State Drive (SSD), or a Universal Flash Storage (UFS) devices that includes the memory device.

25. The electronic system of claim 23, further comprising at least one processor, at least one input device, and at least one output device.