ADAPTIVE SYSTEMS AND PROCEDURES FOR DEFENDING A PROCESSOR AGAINST TRANSIENT FAULT ATTACKS
First Claim
1. A method operational on a processor device, comprising:
- detecting transient faults within the processor device; and
adaptively adjusting a control parameter in response to the detected transient faults to adaptively control an amount of processor device resources devoted to transient fault defense compared to an amount of processor device resources devoted to other operations.
1 Assignment
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Accused Products
Abstract
Various features pertain to defending a smartphone processor or other device from a transient fault attack. In one example, the processor is equipped to detect transient faults using a fault detection system and to adaptively adjust a control parameter in response to the transient faults, where the control parameter controls a physical operation of the processor (such as by gating its clock signal) or a functional operation of the fault detection system (such as a particular Software Fault Sensor (SFS) employed to detect transient faults). In some examples, in response to each newly detected fault, the detection system is controlled to consume more processor time to become more aggressive in detecting additional faults. This serves to quickly escalate fault detection in response to an on-going attack to promptly detect the attack so that the device can be disabled to prevent loss of sensitive information, such as security keys or passcodes.
15 Citations
42 Claims
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1. A method operational on a processor device, comprising:
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detecting transient faults within the processor device; and adaptively adjusting a control parameter in response to the detected transient faults to adaptively control an amount of processor device resources devoted to transient fault defense compared to an amount of processor device resources devoted to other operations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A processor device, comprising:
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a communication interface; a processing circuit coupled to the communication interface, the processing circuit configured to detect transient faults within the processor device; and adaptively adjust a control parameter of the processor device in response to the transient faults to adaptively control an amount of processor device resources devoted to transient fault defense compared to an amount of processor device resources devoted to other operations. - View Dependent Claims (13, 14, 15, 16, 17, 22)
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- 19. The processor device of claim 19, wherein the percentage of time devoted by the processor device to defensive countermeasures is increased during the tracking interval in proportion to a number of new transient faults detected within the tracking interval.
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23. A processor device, comprising:
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means for detecting transient faults within the processor device; and means for adaptively adjusting a control parameter of the processor device in response to the transient faults to adaptively control an amount of processor device resources devoted to transient fault defense compared to an amount of processor device resources devoted to other operations. - View Dependent Claims (24, 25)
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26. A machine-readable storage medium having one or more instructions which when executed by a processing circuit causes the processing circuit to:
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detect transient faults within the processor device; and adaptively adjust a control parameter for transient fault defense of the processor device in response to the transient faults to adaptively control art amount of processor device resources devoted to transient fault defense compared to an amount of processor device resources devoted to other operations. - View Dependent Claims (27, 28)
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29. A method operational on a processor device, comprising:
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detecting transient faults within the processor device; and adaptively adjusting a clock signal of the processor device in response to the transient faults to selectively gate clock cycles. - View Dependent Claims (30, 31, 32, 33, 34)
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35. A processor device, comprising:
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a communication interface; and a processing circuit coupled to the communication interface, the processing circuit configured to detect transient faults within the processor device; and adaptively adjust a clock signal of the processor device in response to the transient faults to selectively gate clock cycles. - View Dependent Claims (36, 37, 38, 39, 40)
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41. A processor device, comprising:
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means for detecting transient faults within the processor device; and means for adaptively adjusting a clock signal of the processor device in response to the transient faults to selectively gate clock cycles.
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42. A machine-readable storage medium having one or more instructions which when executed by a processing circuit causes the processing circuit to:
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detect transient faults within the processor device; and adaptively adjust a clock signal of the processor device in response to the transient faults to selectively gate clock cycles.
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Specification