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NAND STRUCTURE WITH TIER SELECT GATE TRANSISTORS

  • US 20170287566A1
  • Filed: 10/13/2016
  • Published: 10/05/2017
  • Est. Priority Date: 03/31/2016
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a first portion of a NAND string connected to a bit line;

    a second portion of the NAND string connected to a source line; and

    an isolation transistor configured to electrically disconnect the first portion of the NAND string from the second portion of the NAND string during a memory operation, the isolation transistor comprises a first channel length and the first portion of the NAND string comprises a second transistor with a second channel length different from the first channel length.

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