NAND STRUCTURE WITH TIER SELECT GATE TRANSISTORS

• US 20170287566A1
• Filed: 10/13/2016
• Published: 10/05/2017
• Est. Priority Date: 03/31/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Sabde, Jagdish, Pachamuthu, Jayavel, Rabkin, Peter
• Granted Patent: US 9,953,717 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor.

Claims

1. An apparatus, comprising:

a first portion of a NAND string connected to a bit line;

a second portion of the NAND string connected to a source line; and

an isolation transistor configured to electrically disconnect the first portion of the NAND string from the second portion of the NAND string during a memory operation, the isolation transistor comprises a first channel length and the first portion of the NAND string comprises a second transistor with a second channel length different from the first channel length.

2. The apparatus of claim 1, further comprising:

a control circuit configured to detect a programmed data state stored within a memory cell transistor of the second portion of the NAND string and cause the isolation transistor to electrically disconnect the first portion of the NAND string from the second portion of the NAND string during the memory operation based on the programmed data state; and

the second channel length is less than the first channel length.

3. The apparatus of claim 1, further comprising:

a control circuit configured to detect that a programmed data state stored within memory cell transistors of the second portion of the NAND string is greater than a particular threshold voltage and cause the isolation transistor to electrically disconnect the first portion of the NAND string from the second portion of the NAND string during the memory operation in response to detection that the programmed data state is greater than the particular threshold voltage.

4. The apparatus of claim 1, wherein:

the second transistor comprises a programmable transistor and the isolation transistor comprises a non-programmable transistor.

5. The apparatus of claim 1, wherein:

the first portion of the NAND string has a first string length and the second portion of the NAND string has a second string length different from the first string length.

6. The apparatus of claim 5, wherein:

the first string length is less than the second string length.

7. The apparatus of claim 1, wherein:

the memory operation comprises an erase operation.

8. The apparatus of claim 7, wherein:

a gate induced drain leakage current occurs within a channel of the first portion of the NAND string during the erase operation.

9. The apparatus of claim 1, wherein:

the memory operation comprises a programming operation.

10. The apparatus of claim 1, wherein:

the first portion of the NAND string is arranged above the second portion of the NAND string.

11. The apparatus of claim 1, wherein:

the second portion of the NAND string is floated during the memory operation.

12. The apparatus of claim 1, further comprising:

a third portion of the NAND string; and

a second isolation transistor configured to electrically connect the third portion of the NAND string to the first portion of the NAND string during the memory operation.

13. The apparatus of claim 1, wherein:

the second portion of the NAND string comprises a third transistor with a third channel length less than the first channel length.

14. An apparatus, comprising:

a first set of memory cell transistors associated with a NAND string;

a second set of memory cell transistors associated with the NAND string; and

an isolation device arranged between the first set of memory cell transistors and the second set of memory cell transistors, the isolation device configured to electrically isolate the first set of memory cell transistors from the second set of memory cell transistors during a memory operation, the isolation device comprises a first transistor with a first channel length and the first set of memory cell transistors comprises a second transistor with a second channel length less than the first channel length.

15. The apparatus of claim 14, wherein:

the isolation device configured to electrically isolate the first set of memory cell transistors from the second set of memory cell transistors based on programmed data states of the first set of memory cell transistors.

16. The apparatus of claim 14, further comprising:

a control circuit configured to detect that a programmed data state stored within memory cell transistors of the second set of memory cell transistors is less than a particular threshold voltage and cause the isolation device to electrically isolate the first set of memory cell transistors from the second set of memory cell transistors during the memory operation in response to detection that the programmed data state is less than the particular threshold voltage.

17. The apparatus of claim 14, wherein:

the isolation device comprises an NMOS transistor.

18. The apparatus of claim 14, wherein:

the first set of memory cell transistors comprises a first number of transistors and the second set of memory cell transistors comprises a second number of transistors greater than the first number of transistors.

19. The apparatus of claim 14, wherein:

the memory operation comprises a programming operation; and

the first set of memory cell transistors comprise charge trap transistors.

20. A method, comprising:

setting a tier select gate transistor arranged between a first set of memory cell transistors of a NAND string and a second set of memory cell transistors of the NAND string into a non-conducting state during a memory operation; and

applying a selected word line voltage to a second memory cell transistor of the second set of memory cell transistors during the memory operation, the tier select gate transistor comprises a non-programmable transistor, the tier select gate transistor comprises a first channel length and the first set of memory cell transistors comprises a second transistor of a second channel length less than the first channel length.