System and Method for Erase Detection before Programming of a Storage Device

• US 20170287568A1
• Filed: 03/29/2016
• Published: 10/05/2017
• Est. Priority Date: 03/29/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Yang, Nian Niles, Yip, Chris, Shah, Grishma
• Granted Patent: US 9,792,998 B1
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step

Abstract

Systems and methods for detecting program disturb and for programming/reading based on the detected program disturb are disclosed. Program disturb comprises unintentionally programming an unselected section of memory during the program operation of the selected section of memory. To reduce the effect of program disturb, the section of memory is analyzed in a predetermined state (such as the erase state) for program disturb. In response to identifying signs of program disturb, the voltages used to program the section of memory (such as the program verify levels for programming data into the cells of the section of memory) may be adjusted. Likewise, when reading data from the section of memory, the read voltages may be adjusted based on the adjusted voltages used for programming. In this way, using the adjusted programming and reading voltages, the effect of program disturb may be reduced.

Claims

1. A method for operating a storage device comprising:

determining to program multiple bits into cells of a section of memory, the multiple bits being represented by at least an erase state, a first programmed state and a second programmed state, wherein the first programmed state and the second programmed state are different from the erase state;

determining an indication of program disturb in the section of memory in the storage device;

determining, based on the indication, an adjusted programming voltage for programming the second programmed state in the section of memory, the adjusted programming voltage for programming the second programmed state being offset from a programming voltage for programming the second programmed state in an absence of detectable program disturb in the section of memory;

determining a programming voltage for programming the first programmed state in the section of memory in the absence of detectable program disturb in the section of memory;

programming data into the section of memory based on the determined adjusted programming voltage for programming the second programmed state and based on the determined programming voltage for programming the first programmed state; and

responsive to a command to read part or all of the data programmed into the section of memory, reading, using a read voltage adjusted based on the determined adjusted programming voltage for programming the programming state and the determined programming voltage for programming the first programming state, the data from the section of memory.

2. The method of claim 1, wherein determining the indication of program disturb comprises accessing a table correlating respective sections of memory with respective indications of program disturb.

4. The method of claim 1, wherein the indication of program disturb comprises an offset voltage, the offset voltage comprising an offset to the programming voltage for programming the second programmed state in the absence of detectable program disturb in the section of memory;

and

wherein determining the adjusted programming voltage for programming the second programmed state in the section of memory comprises adding the offset voltage to the programming voltage for programming the second programmed state in the absence of detectable program disturb in the section of memory.

5. The method of claim 1, wherein the indication of program disturb is based on an analysis of the erase state for one or more cells in the section of memory.

6. The method of claim 5, wherein determining the indication of program disturb comprises:

counting a number of bits in the cells of a wordline in the erase state that are greater than a predetermined threshold; and

based on the number of bits greater than the predetermined threshold, determining the indication of program disturb.

9. The method of claim 1, further comprising, responsive to receipt of the command to read part or all of the data programmed into the section of memory, accessing the determined adjusted programming voltage from a table.

3. A method for operating a storage device comprising:

accessing a table comprises entries correlating groups of blocks to groups of wordlines, wherein a first correlated program disturb for a group of blocks to a first group of wordlines comprises no indication of program disturb and wherein a second correlated program disturb for the first correlated group of blocks to a second group of wordlines comprises an indication of program disturb;

determining programming voltages in an absence of detectable program disturb for programming the first group of wordlines;

determining, based on the indication of program disturb, adjusted programming voltages for programming the second group of wordlines in the group of blocks of memory, the adjusted programming voltages being different from the programming voltages in the absence of detectable program disturb in the group of blocks of memory;

programming data into the first group of wordlines and second group of wordlines in a block of memory based on the programming voltages and the adjusted programming voltages, respectively; and

responsive to a command to read part or all of the data programmed into the first group of wordlines and second group of wordlines of the block of memory, reading, based on the programming voltages and the adjusted programming voltages, respectively, the data from the first group of wordlines and second group of wordlines in the block of memory.

22. The method of claim 3, wherein the indication of program disturb comprises a first indication of program disturb and a second indication of program disturb;

wherein the first indication of program disturb is used to determine a first voltage offset voltage indicative of a difference from program voltage verification absent the program disturb;

wherein the second indication of program disturb is used to determine a second voltage offset voltage indicative of a difference from program voltage verification absent the program disturb; and

wherein the first voltage offset is different from the second voltage offset

23. The method of claim 3, wherein the table correlates blocks in the storage device with wordlines within respective blocks.

25. The method of claim 3, wherein a highest wordline in a respective group of the wordlines is analyzed to determine a voltage offset for programming the respective group of the wordlines.

28. The method of claim 3, wherein the first group of wordlines includes wordline 0.

7-8. -8. (canceled)

10-11. -11. (canceled)

12. A storage device comprising:

erase state analysis circuitry configured to analyze an erase state of at least a part of a wordline in the storage device in order to determine an indication of program disturb in the at least a part of the wordline, wherein the wordline has multiple bits therein being represented by at least an erase state, a first programmed state and a second programmed state;

programming determination circuitry configured to determine programming voltages for programming multiple bits into the storage device, the programming determination circuitry configured to determine;

a programming voltage for programming the first programmed state in the section of memory in the absence of detectable program disturb in the section of memory; and

an adjusted programming voltage, based on the determined indication of the program disturb, for programming the second programmed state, the adjusted programming voltage being offset from programming the second programming state in an absence of the indication of program disturb;

programming circuitry configured to program the wordline based on the programming voltage for programming the first programmed state and the adjusted programming voltage for programming the second programmed state; and

read circuitry configured to read using a read voltage based on the determined programming voltage for programming the first programmed state and the adjusted programming voltage for programming the second programmed state.

13. The storage device of claim 12, wherein the erase state analysis circuitry is configured to:

count a number of bits in cells of the wordline in the erase state that are greater than a predetermined threshold; and

based on the number of bits greater than the predetermined threshold, determine the indication of program disturb.

14. (canceled)

15. A storage device comprising:

erase state analysis circuitry configured to analyze an erase state of at least a part of memory in the storage device in order to determine an indication of program disturb in the at least a part of the memory;

programming adjustment circuitry configured to adjust program verify voltage levels, based on the determined indication of the program disturb, for all of a plurality of states except for an erase state;

programming circuitry configured to program the part of memory based on the adjusted program verify voltage levels for all of the plurality of states except for the erase state; and

read circuitry configured to read using a read voltage adjusted based on the adjusted program verify voltage levels.

16. (canceled)

17. A storage device comprising:

a memory; and

a controller in communication with the memory, the controller configured to;

determine to program multiple bits of data in cells in a section of memory, the multiple bits of data being represented by an erase state and additional states;

determine program disturb for the section of the memory;

adjust program verify voltage levels for each of the additional states based on the determined program disturb without adjusting the erase state;

program, using the adjusted program verify voltage levels for each of the additional states without adjusting the erase state, data in the section of the memory; and

read, using a read voltage based on the program verify voltage levels for each of the additional states without adjusting the erase state, the data from the section of memory.

18. The storage device of claim 17, wherein the controller is configured to determine the program disturb for a section of the memory by accessing a table, the table indicative of previous analysis of the section of memory for the program disturb.

19. The storage device of claim 17, wherein the controller is configured to determine the program disturb for a section of the memory by analyzing a state of the section of memory.

20. The storage device of claim 19, wherein the state comprises the erase state of one or more cells in the section of memory.

21. The storage device of claim 19, wherein the controller is configured to analyze the state of the section of memory by comparing the state of the section of memory against a predetermined voltage;

and

wherein the controller is configured to adjust programming of the section of the memory based on the comparison.

29. The storage device of claim 17, wherein the adjust program verify voltage levels for each of the additional states are uniformly adjusted.

30. The storage device of claim 17, wherein the adjust program verify voltage levels for each of the additional states are non-uniformly adjusted.

24. (canceled)

26. (canceled)

27. (canceled)