CHIP PACKAGING METHOD AND PACKAGE STRUCTURE

• US 20170287797A1
• Filed: 09/10/2015
• Published: 10/05/2017
• Est. Priority Date: 09/12/2014
• Status: Active Grant

• Current Assignee: China Wafer Level CSP Co., Ltd.
• Original Assignee: China Wafer Level CSP Co., Ltd.
• Inventors: Wang, Zhiqi, Yu, Qiong, Wang, Wei
• Granted Patent: US 10,090,217 B2
• Time in Patent Office: Days
• CPC Class Codes: G06V 40/1306 non-optical, e.g. ultrasonic or capacitive sensing
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/24246 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45184 Tungsten (W) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/08 the material being an electrical insulator, e.g. glass
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/32 : Holders for supporting the complete device in operation, i.e. detachable fixtures H01L23/40 takes precedence
• CPC Class Codes: H01L 23/498 : Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/585 : comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10155 : being other than a cuboid
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A chip packaging method and package structure, the package structure including a substrate, a sensing chip coupled to the substrate, a plastic package layer located on the substrate, and a covering layer located on the plastic package layer and a first surface of the sensing chip; the sensing chip including the first surface and a second surface opposite to the first surface, and further including a sensing area located on the first surface; the second surface of the sensing chip faces towards the substrate; and the plastic package layer encloses the sensing chip, and the surface of the plastic package layer is flush with the first surface of the sensing chip.

Claims

1. A chip package structure, comprising:

a substrate;

a sensing chip coupled to the substrate, wherein the sensing chip comprises a first surface and a second surface opposite to the first surface, the sensing chip further comprises a sensing region located on the first surface, and the second surface of the sensing chip faces the substrate;

a plastic packaging layer located on the substrate, wherein the plastic packaging layer surrounds the sensing chip, and the surface of the plastic packaging layer is flush with the first surface of the sensing chip; and

a cover layer located on the plastic packaging layer and the first surface of the sensing chip.

2. The chip package structure according to claim 1, wherein the sensing chip further comprises:

a peripheral region located on the first surface and surrounding the sensing region;

an edge groove located in the peripheral region, wherein the edge groove is exposed on a side surface of the sensing chip; and

a chip circuit located on a surface of the peripheral region of the sensing chip and on a side wall and a bottom surface of the edge groove.

3. The chip package structure according to claim 2, wherein the plastic packaging layer is further located in the edge groove, and is flush with a surface of the sensing region of the sensing chip.

4. The chip package structure according to claim 2, further comprising a first pad located at the bottom of the edge groove, wherein the chip circuit is electrically connected to the first pad.

5. The chip package structure according to claim 4, wherein the substrate comprises a first side surface, the first side surface of the substrate is provided with a second pad, and the sensing chip is coupled to the second pad.

6. The chip package structure according to claim 1, wherein the substrate is provided with a connection portion, and the connection portion is configured to electrically connect the sensing chip to an external circuit.

7. The chip package structure according to claim 5, further comprising a conductive wire, wherein two ends of the conductive wire are connected to the first pad and the second pad respectively, a point on the conductive wire whose distance to the first side surface of the substrate is maximal is an apex, and the apex is lower than the surface of the plastic packaging layer.

8. The chip package structure according to claim 5, further comprising a conductive layer located on the surface of the side wall of the sensing chip, on the first side surface of the substrate, and in the edge groove, wherein two ends of the conductive layer are electrically connected to the first pad and the second pad respectively.

9. The chip package structure according to claim 1, wherein a thickness of the cover layer ranges from 20 microns to 100 microns, an Mohs hardness of the cover layer is greater than or equal to 8H, and a dielectric constant of the cover layer is greater than or equal to 7.

10. The chip package structure according to claim 1, wherein the cover layer is made of at least one of an inorganic nanometer material or a polymer material.

11. The chip package structure according to claim 10, wherein the polymer material comprises at least one of epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer and polyvinyl alcohol.

12. The chip package structure according to claim 10, wherein the inorganic nanometer material comprises at least one of aluminium oxide and cobalt oxide.

13. The chip package structure according to claim 1, wherein the cover layer comprises a glass substrate, and the glass substrate has a dielectric constant ranging from 6 to 10 and a thickness ranging from 100 microns to 300 microns;

or the cover layer comprises a ceramic substrate, and the ceramic substrate has a dielectric constant ranging from 20 to 100 and a thickness ranging from 100 microns to 200 microns.

14. The chip package structure according to claim 1, wherein the plastic packaging layer is made of polymer.

15. The chip package structure according to claim 14, wherein the polymer comprises at least one of epoxy resin, polyethylene, polypropylene, polyolefin, polyamide, and polyurethane.

16. The chip package structure according to claim 1, further comprising a guard ring on the substrate, wherein the guard ring surrounds the sensing chip, the plastic packaging layer and the cover layer, and a part of the cover layer over the sensing region is exposed from the guard ring.

17. The chip package structure according to claim 16, further comprising a housing surrounding the plastic packaging layer, the sensing chip and the cover layer, wherein a part of the cover layer over the sensing region is exposed from the housing.

18. A chip packaging method, comprising:

providing a substrate;

coupling a sensing chip to the substrate, wherein the sensing chip comprises a first surface and a second surface opposite to the first surface, the sensing chip further comprises a sensing region located on the first surface, and the second surface of the sensing chip faces the substrate;

forming a plastic packaging layer on the substrate, wherein a surface of the plastic packaging layer is flush with the first surface of the sensing chip; and

forming a cover layer on the plastic packaging layer and the first surface of the sensing chip.

19. The chip packaging method according to claim 18, wherein a thickness of the cover layer ranges from 20 microns to 100 microns, an Mohs hardness of the cover layer is greater than or equal to 8H, and a dielectric constant of the cover layer is greater than or equal to 7.

20. The chip packaging method according to claim 18, wherein the plastic packaging layer is made of a polymer material.

21. The chip packaging method according to claim 20, wherein the plastic packaging layer is formed by a transfer injecting process, a screen printing process, a spin coating process or a spraying coating process.

22. The chip packaging method according to claim 18, wherein the cover layer is made of at least one of an inorganic nanometer material or a polymer material.

23. The chip packaging method according to claim 22, wherein the polymer material comprises at least one of epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer and polyvinyl alcohol.

24. The chip packaging method according to claim 23, wherein the cover layer is formed by a screen printing process, a spin coating process, or a spraying coating process.

25. The chip packaging method according to claim 22, wherein the inorganic nanometer material comprises at least one of aluminium oxide and cobalt oxide.

26. The chip packaging method according to claim 25, wherein the cover layer is formed by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a screen printing process, a spin coating process, or a spray coating process.

27. The chip packaging method according to claim 18, wherein before coupling the sensing chip to the substrate, the chip packaging method further comprises:

forming a first adhesive layer on a first side surface of the substrate or a second surface of the sensing chip; and

fixing the sensing chip to the first side surface of the substrate via the first adhesive layer.

28. The chip packaging method according to claim 18, further comprising:

forming a second adhesive layer on the plastic packaging layer and the first surface of the sensing chip; and

forming the cover layer on the second adhesive layer.

29. The chip packaging method according to claim 18, wherein the sensing chip further comprises a peripheral region located on the first surface and surrounding the sensing region, and the method further comprises:

forming an edge groove in the peripheral region of the sensing chip before forming the plastic packaging layer, wherein the edge groove is exposed from a side surface of the sensing chip; and

forming a chip circuit on a surface of the peripheral region and on a side wall and a bottom surface of the edge groove.

30. The chip packaging method according to claim 29, wherein the plastic packaging layer is further formed in the edge groove, and is flush with a surface of the sensing region of the sensing chip.

31. The chip packaging method according to claim 29, further comprising:

forming a first pad at the bottom of the edge groove, wherein the chip circuit is electrically connected to the first pad.

32. The chip packaging method according to claim 31, wherein the substrate comprises a first side surface, the first side surface of the substrate is provided with a second pad, the method further comprises forming a conductive wire before forming the plastic packaging layer, two ends of the conductive wire are connected to the first pad and the second pad respectively, a point on the conductive wire whose distance to the first side surface of the substrate is maximal is an apex, and the apex is lower than the surface of the plastic packaging layer.

33. The chip packaging method according to claim 31, wherein the substrate comprises a first side surface, the first side surface of the substrate is provided with a second pad, the method further comprises forming a conductive layer on a side wall of the sensing chip, on the first side surface of the substrate, and in the edge groove, and two ends of the conductive layer are electrically connected to the first pad and the second pad respectively.