LOCALIZED HIGH DENSITY SUBSTRATE ROUTING

• US 20170287831A1
• Filed: 06/12/2017
• Published: 10/05/2017
• Est. Priority Date: 09/28/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Starkston, Robert, Mallik, Debendra, Guzek, John S., Chiu, Chia-Pin, Kulkarni, Deepak, Mahajan, Ravindranath V.
• Granted Patent: US 10,366,951 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/206 : Length ranges

Abstract

Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

Claims

1. A method of forming an interconnect element to connect between two dies, the method comprising:

forming a first layer of a medium including one of glass, ceramic, or silicon;

forming first high density interconnect routing in the first layer;

forming a second layer of the medium in contact with the first layer;

forming second high density interconnect routing in the second layer, the second high density interconnect routing electrically connected to the first high density interconnect routing;

forming a third layer of the medium, the second layer situated between the first and third layers;

forming third high density interconnect routing in the third layer, wherein the interconnect element includes only three layers with high density interconnect routing;

forming first and second pads at a first surface of the medium in electrical contact with the third high density interconnect routing, the first and second pads at least partially exposed at a first surface of the medium; and

electrically connecting first and second dies to the first and second pads, respectively, and the first and second dies to low density interconnect routing of a substrate to which the first die is electrically coupled.

2. The method of claim 1, wherein the first, second, and third layers of the high density interconnect routing include routing that is up to about 100 times more dense than routing in the substrate.

3. The method of claim 1, wherein the first high density interconnect routing includes:

a first via electrically coupled to a pad of the first pads;

a second via electrically coupled to a pad of the second pads; and

a trace electrically connected to the first via and to the second via.

4. The method of claim 1, wherein the first pads include an exposed footprint with an area larger than a corresponding footprint of a via to connect to a pad of the first die.

5. The method of claim 1, herein the medium includes silicon.

6. The method of claim 5, wherein the medium includes one or more layers of glass or ceramic.

7. The method of claim 1, wherein the medium includes a second surface opposite the first surface, wherein the second surface is an inactive surface with no electrical connectivity to the high density routing available through the second surface.

8. A method of forming an apparatus comprising:

forming a medium including low density interconnect routing therein;

forming an interconnect element including first, second, and third layers of high density interconnect routing therein, the second layer of high density interconnect routing situated between the first and third layers of high density interconnect routing, the first, second, and third layers of high density interconnect routing including a plurality of electrically conductive members, an electrically conductive member of the plurality of electrically conductive members electrically connecting the first via to the second via;

embedding the interconnect element in the medium;

forming a dielectric layer over the interconnect element;

forming first and second vias in the dielectric layer, the first and second vias passing through the dielectric layer; and

forming solder resist over the dielectric layer, the solder resist not fully covering the first and second vias.

9. The method of claim 8, wherein the first, second, and third layers of high density interconnect routing include routing that is up to about 100 times more dense than the low density interconnect routing in the medium.

10. The method of claim 8, wherein forming the interconnect element further includes:

forming a third via in the third layer of high density interconnect routing;

forming a first pad at least partially exposed by a surface of the interconnect element;

electrically coupling the third via to the first pad;

forming a fourth via in the third layer of high density interconnect routing;

forming a second pad at least partially exposed by the surface of the interconnect element;

electrically coupling the fourth via to the second pad; and

forming a trace, the trace electrically connecting the first via and the second via.

11. The method of claim 8, wherein the first pad includes an exposed footprint with an area larger than a corresponding footprint of the first via.

12. The method of claim 8, wherein the interconnect element includes silicon.

13. The method of claim 12, wherein the interconnect element includes one or more layers of glass or ceramic.

14. The method of claim 8, wherein the interconnect element includes a second surface opposite the first surface, wherein the second surface is an inactive surface with no electrical connectivity to the first, second, and third layers of high density interconnect routing available through the second surface.

15. A method of forming a package comprising:

forming an interconnect die including first, second, and third layers of high density interconnect routing therein, the second layer of high density interconnect routing situated between the first and third layers of high density interconnect routing, the high density interconnect routing including an electrically conductive member, the interconnect die including first and second electrically conductive pads, on or at least partially in, a top surface of the interconnect die, the electrically conductive member electrically connecting the first electrically conductive via to the second electrically conductive via through the first and second electrically conductive pads;

connecting, by an adhesive material the interconnect die to a substrate, the substrate including low density interconnect routing therein;

forming first and second electrically conductive vias in a dielectric layer of the substrate, the first and second electrically conductive vias electrically coupled to the first and second pads, respectively; and

electrically coupling first and second dies to the first and second pads, respectively.

16. The method of claim 15, further comprising:

forming a metal pad on or at least partially in a top surface of the substrate, wherein the adhesive layer connects the interconnect die to the metal pad.

17. The method of claim 15, wherein a footprint of the metal pad is greater than or equal to a footprint of the interconnect die.

18. The method of claim 15, wherein the first, second, and third layers of high density interconnect routing include routing that is up to about 100 times more dense than the low density interconnect routing in the substrate.

19. The method of claim 18, wherein the interconnect die includes a bottom surface opposite the top surface, wherein the bottom surface is an inactive surface with no electrical connectivity to the first, second, and third layers of high density interconnect routing available through the bottom surface.

20. The method of claim 17, wherein the first pad includes an exposed footprint with an area larger than a corresponding footprint of the first via.