FAN-OUT SEMICONDUCTOR PACKAGE

• US 20170287853A1
• Filed: 09/28/2016
• Published: 10/05/2017
• Est. Priority Date: 03/31/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: KIM, Han, HAN, Mi Ja, HUR, Kang Heon, KO, Young Gwan
• Granted Patent: US 10,373,884 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/642 : Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate

Abstract

The fan-out semiconductor package includes: a semiconductor chip having an active surface having a connection pad disposed thereon and an inactive surface disposed to oppose the active surface; a first capacitor disposed adjacently to the semiconductor chip; an encapsulant at least partially encapsulating the first connection member and the semiconductor chip; a first connection member disposed on the encapsulant, the first capacitor, and the semiconductor chip, and a second capacitor disposed on the other surface of the first connection member opposing one surface of the first connection member on which the semiconductor chip is disposed, wherein the first connection member includes a redistribution layer electrically connected to the connection pad of the semiconductor chip, the first capacitor, and the second capacitor, and the first capacitor and the second capacitor are electrically connected to the connection pad through a common power wiring of the redistribution layer.

Claims

1. A fan-out semiconductor package comprising:

a semiconductor chip having an active surface having a connection pad disposed thereon and an inactive surface disposed to oppose the active surface;

a first capacitor disposed adjacently to the semiconductor chip;

an encapsulant at least partially encapsulating the first connection member and the non-active surface of the semiconductor chip;

a first connection member disposed on the encapsulant, the first capacitor, and the active surface of the semiconductor chip, and

a second capacitor disposed on the other surface of the first connection member opposing one surface of the first connection member on which the semiconductor chip is disposed,

wherein the first connection member includes a redistribution layer electrically connected to the connection pad of the semiconductor chip, the first capacitor, and the second capacitor, and

the first capacitor and the second capacitor are electrically connected to the connection pad of the semiconductor chip through a common power wiring of the redistribution layer.

2. The fan-out semiconductor package of claim 1, wherein C₁ is equal to C₂, in which C₁ and C₂ are capacitances of the first and second capacitors, respectively.

3. The fan-out semiconductor package of claim 1, wherein t₁ is greater than t₂, in which t₁ and t₂ are thicknesses of the first and second capacitors, respectively.

4. The fan-out semiconductor package of claim 1, wherein L₁ is equal to L₂, in which L₁ and L₂ are equivalent series inductances (ESL) of the first and second capacitors, respectively.

5. The fan-out semiconductor package of claim 1, wherein R₁ is equal to R₂, in which R₁ and R₂ are equivalent series resistances (ESR) of the first and second capacitors, respectively.

6. The fan-out semiconductor package of claim 1, wherein the first and second capacitors are connected to each other in parallel.

7. The fan-out semiconductor package of claim 1, further comprising a passivation layer disposed on the other surface of the first connection member opposing one surface of the first connection member on which the semiconductor chip is disposed and having openings exposing at least a portion of a wiring of the redistribution layer,

wherein the second capacitor is disposed on a surface of the passivation layer.

8. The fan-out semiconductor package of claim 7, further comprising connection terminals disposed in the openings of the passivation layer,

wherein the connection terminals are disposed to surround the second capacitor.

9. The fan-out semiconductor package of claim 1, further comprising a second connection member having a through-hole,

wherein the semiconductor chip and the first capacitor are disposed in the through-hole, and

a portion of the encapsulant encapsulates at least a portion of the second connection member.

10. The fan-out semiconductor package of claim 9, wherein the second connection member includes a first insulating layer, a first redistribution layer contacting the first connection member and embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, and

the first and second redistribution layers are electrically connected to the connection pad.

11. The fan-out semiconductor package of claim 10, wherein the second connection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and

the third redistribution layer is electrically connected to the connection pad.

12. The fan-out semiconductor package of claim 10, wherein a distance between the redistribution layer of the first connection member and the first redistribution layer is greater than that between the redistribution layer of the first connection member and the connection pad.

13. The fan-out semiconductor package of claim 10, wherein the first redistribution layer is thicker than the redistribution layer of the first connection member.

14. The fan-out semiconductor package of claim 10, wherein a lower surface of the first redistribution layer is disposed on a level above a lower surface of the connection pad.

15. The fan-out semiconductor package of claim 11, wherein the second redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

16. The fan-out semiconductor package of claim 9, wherein the second connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on both surfaces of the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and

the first to third redistribution layers are electrically connected to the connection pad.

17. The fan-out semiconductor package of claim 16, wherein the second connection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and

the fourth redistribution layer is electrically connected to the connection pad.

18. The fan-out semiconductor package of claim 16, wherein the first insulating layer is thicker than the second insulating layer.

19. The fan-out semiconductor package of claim 16, wherein the third redistribution layer is thicker than the redistribution layer of the first connection member.

20. The fan-out semiconductor package of claim 16, wherein the first redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

21. The fan-out semiconductor package of claim 16, wherein a lower surface of the third redistribution layer is disposed on a level below a lower surface of the connection pad.