SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF

• US 20170287881A1
• Filed: 12/26/2016
• Published: 10/05/2017
• Est. Priority Date: 03/31/2016
• Status: Abandoned Application

• Current Assignee: Kaistar Lighting (Xiamen) Co.,Ltd.
• Original Assignee: Kaistar Lighting (Xiamen) Co.,Ltd.
• Inventors: Yang, Weihong, Lin, Shenbo, Huang, Zhiwei
• Application Number:
  US15/390,555
• Publication Number:
  US 20170287881A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 2933/0075 relating to heat extraction or cooling elements
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/64 Heat extraction or cooling elements

Abstract

A semiconductor element and a manufacturing method thereof are provided. The semiconductor element includes a substrate and multiple semiconductor chips disposed thereon. The semiconductor chips are arranged to form multiple sequentially nested circle(s), and a circumference of each of which is arranged with multiple the semiconductor chips. The numbers of the semiconductor chips arranged on the respective circumferences of the sequentially nested circle(s) from inside to outside are gradually increased, and distances among the circumferences are gradually decreased from inside to outside. The disclosure optimizes the arrangement of the semiconductor chips to make the arrangement of the semiconductor chips be loose in the central region while more dense towards outside, which is in favor of uniform heat distribution and therefore can slow down aging and failure of the semiconductor chips and improve heat dissipation performance and light emitting effect of product.

Claims

1. A semiconductor element comprising a substrate and a plurality of semiconductor chips disposed on the substrate;

wherein the plurality of semiconductor chips are arranged to form a plurality of sequentially nested circle(s), and the circumference of each of the circle(s) is arranged with a plurality of the semiconductor chips thereon;

numbers of the semiconductor chips arranged on the respective circumferences of the plurality of sequentially nested circle(s) from inside to outside are gradually increased, and distances of every adjacent two of the circumferences of the plurality of sequentially nested circle(s) from inside to outside are gradually decreased.

2. The semiconductor element according to claim 1, wherein the center of the circle(s) is arranged with the semiconductor chip, and on any one connecting line from the center to the outmost circumference, distances from the circumferences of the plurality of sequentially nested circle(s) to the center satisfy a relationship that:

R₁≧

(R₂−

R₁)≧

(R₃−

R₂)≧

. . . ≧

(R_N−

R<sub>N−

1</sub>)>

b;

where R₁, R₂, R₃, . . . , R<sub>N−

1</sub> and R_N are the distances from the circumferences of the plurality of sequentially nested circle(s) to the center on the connecting line respectively, wherein b is a width of the plurality of semiconductor chips and a length of the plurality of semiconductor chips is larger than or equal to b, wherein N is a natural number and a value of N depends on the total amount of the plurality of semiconductor chips.

3. The semiconductor element according to claim 1, wherein the center of the circle(s) does not be arranged with the semiconductor chip, and on any one connecting line from the center to the outmost circumference, distances from the respective circumferences of the plurality of sequentially nested circle(s) to the center satisfy a relationship that:

2 R₁≧

(R₂−

R₁)≧

(R₃−

R₂)≧

. . . ≧

(R_N−

R<sub>N−

1</sub>)>

b;

where R₁, R₂, R₃, . . . , R<sub>N−

1</sub> and R_N respectively are the distances from the respective circumferences of the plurality of sequentially nested circle(s) to the center on the connecting line, wherein b is a width of the plurality of semiconductor chips and a length of the plurality of semiconductor chips is larger than or equal to b, wherein N is a natural number and a value of N depends on the total amount of the plurality of semiconductor chips.

4. The semiconductor element according to claim 1, wherein a minimum radian between two adjacent semiconductor chips on an Nth circumference from inside to outside is c, and a minimum radian between two adjacent semiconductor chips on an (N−

1)th circumference from inside to outside is d, and c and d satisfy that;

d≧

c.

5. The semiconductor element according to claim 1, wherein heat dissipation spaces of respective semiconductor chips on any one connecting line from a center of the circle(s) to the outmost circumference along a direction from inside to outside are gradually decreased;

wherein the heat dissipation space of a semiconductor is defined as a circular region with the geometrical center of the chip as the center and the minimum one of the distances of the center to an adjacent chip and to the edge of the die bonding region as the radius.

6. The semiconductor element according to claim 1, wherein the substrate is a mirror aluminum substrate or a ceramic substrate.

7. The semiconductor element according to claim 1, wherein the semiconductor chips are light-emitting diode chips.

8. A manufacturing method of a semiconductor element, wherein it comprises steps:

setting a target circular region on a substrate according to a radius of a die bonding region;

placing predetermined number of semiconductor chips in the target circular region on the substrate in a form of equidistant arrangement;

according to left and right remaining spaces of each row of semiconductor chips in the target circular region, increasing spaces on the row direction among semiconductor chips in the row of the semiconductor chips, wherein increased proportions of the spaces for the semiconductor chips are decreased along directions towards two ends of the row;

according to upper and lower remaining spaces in the target circular region, increasing spaces on the column direction between semiconductor chips in each two adjacent rows of semiconductor chips, increased proportions of the spaces for the semiconductor chips are decreased along directions towards two ends of the two adjacent rows; and

according to a rule that heat dissipation spaces of respective semiconductor chips in the predetermined number of semiconductor chips are gradually decreased from a center to an outmost circumference, slightly adjusting positions of the predetermined number of semiconductor chips, wherein the heat dissipation space of each the semiconductor chip is defined as a circular region with a center of the semiconductor chip as a center and the minimum one of distances from the center to an adjacent semiconductor chip and to an edge of the die bonding region as a radius.

9. The manufacturing method of a semiconductor element according to claim 8, wherein the substrate is a mirror aluminum substrate or a ceramic substrate.

10. The manufacturing method of a semiconductor element according to claim 8, wherein the semiconductor chips are light-emitting diode chips.