DEVICE STRUCTURE AND MANUFACTURING METHOD USING HDP DEPOSITED SOURCE-BODY IMPLANT BLOCK

• US 20170288034A1
• Filed: 04/27/2017
• Published: 10/05/2017
• Est. Priority Date: 04/30/2007
• Status: Active Grant

• Current Assignee: Anup Bhalla, Francois Hebert, Sik K. Lui, Sung-Shan Tai
• Original Assignee: Francois Hebert
• Inventors: Bhalla, Anup, Hbert, Franois, Tai, Sung-Shan, Lui, Sik K.
• Granted Patent: US 10,896,968 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform

Abstract

This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

Claims

1. A method for manufacturing a trenched semiconductor power device comprising:

opening a plurality of trenches from a top surface of a semiconductor substrate and forming a gate insulation layer on sidewalls and bottom surface of said trenches;

forming an implanting-ion block above said top surface in a mesa area at a distance away from said trenches for blocking body implanting ions and source ions from entering into said substrate under said mesa area whereby masks for manufacturing said semiconductor power device can be reduced; and

implanting body ions into said semiconductor substrate with said implanting-ion block blocking said mesa area and diffusing said body ions into a body region with said body region separated as two separated body regions disposed on two opposite sides of said trenches.

2. The method of claim 1 further comprising:

forming trenched gate in each of said trenches as a split gate including a lower gate segment covered by an insulation layer and an upper gate segment above said insulation layer.

3. The method of claim 1 further comprising:

applying a HDP deposition process to form a thick oxide layer on bottom surface of said trenches simultaneously with and implanting ion blocks as HDP oxide layer and forming split gate in each of said trenches.

4. A trenched semiconductor power device comprising a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near said top surface above a drain region disposed on a bottom surface of a substrate, wherein said semiconductor power device further comprising:

an implanting-ion block disposed above said top surface on a mesa area next to said body region having a thickness substantially for blocking body implanting ions from entering into said substrate under said mesa area whereby masks for manufacturing said semiconductor power device can be reduced; and

5. The trenched power semiconductor power device of claim 4 further comprising:

a termination area wherein said implanting-ion block having a greater width than said implanting-ion block on said mesa area for separating said body regions and forming floating body regions in said termination area to form at least a guard ring in a trenched gate surrounded by said floating body region in said termination area.

6. The trenched power semiconductor power device of claim 4 further comprising:

an integrated Schottky field effect transistor (FET) including a body dopant region, with a higher dopant concentration than said body region, disposed adjacent to said source region, and said body dopant region having a region boundary substantially aligned with said ion-implanting block.

7. The trenched power semiconductor power device of claim 4 wherein:

said trenched gate further comprising a split gate including a lower gate segment covered by an insulation layer and an upper gate segment above said insulation layer.

8. The trenched power semiconductor power device of claim 4 wherein:

said trenched gate further comprising a split gate including a lower gate segment covered by an insulation layer and an upper gate segment above said insulation layer.; and

said trenched gate further including a thick oxide layer disposed on a bottom surface of said trenched gate having a thickness greater than a gate oxide layer padding sidewalls of said trenched gate.

9. The trenched power semiconductor power device of claim 4 wherein:

said thick oxide layer disposed on said bottom of said trenched gate is a high-density plasma (HDP) deposited thick oxide layer and said implanting-ion block further comprising a HDP deposited oxide layer formed simultaneously with said thick oxide layer disposed on said bottom of said trenched gate.