Aluminum Nitride Based Silicon-On-Insulator Substrate Structure

• US 20170288055A1
• Filed: 03/28/2017
• Published: 10/05/2017
• Est. Priority Date: 03/29/2016
• Status: Active Grant

• Current Assignee: Qromis, Inc.
• Original Assignee: Quora Technology, Inc.
• Inventors: Aktas, Ozgur, Odnoblyudov, Vladimir, Risbud, Dilip, Basceri, Cem
• Granted Patent: US 10,755,986 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A substrate structure includes a polycrystalline substrate, a plurality of thin film layers disposed on the polycrystalline substrate, a bonding layer coupled to at least a portion of the plurality of thin films, and a single crystal silicon layer joined to the bonding layer.

Claims

1. A substrate structure comprising:

a polycrystalline substrate;

a plurality of thin film layers disposed on the polycrystalline substrate;

a bonding layer coupled to at least a portion of the plurality of thin films; and

a single crystal silicon layer joined to the bonding layer.

2. The substrate structure of claim 1 further comprising:

a plurality of laterally diffused MOSFET (LDMOS) devices coupled to the single crystal silicon layer.

3. The substrate structure of claim 1 wherein the single crystal silicon layer comprises an exfoliated silicon layer having a (100) crystalline orientation.

4. The substrate structure of claim 1 wherein the polycrystalline substrate comprises polycrystalline aluminum nitride.

5. The substrate structure of claim 4 wherein the plurality of thin film layers comprises:

an adhesion layer coupled to the polycrystalline substrate; and

a barrier layer coupled to the adhesion layer.

6. The substrate structure of claim 5 wherein:

the adhesion layer comprises a tetraethyl orthosilicate (TEOS) layer encapsulating the polycrystalline substrate; and

the barrier layer comprises a silicon nitride layer encapsulating the TEOS layer.

7. The substrate structure of claim 1 wherein the bonding layer comprises silicon oxide and has a thickness of 1 μ

m or less.

8. The substrate structure of claim 7 wherein the bonding layer has a thickness of 300 nm or less, 100 nm or less, or 30 nm or less.

9. The substrate structure of claim 1 wherein a thermal resistance of the polycrystalline substrate is less than about 40 K/W.

10. The substrate structure of claim 1 wherein a thermal conductivity of the polycrystalline substrate is greater than about 150 W/(m·

K).

11. The substrate structure of claim 1 wherein an RF absorption coefficient of the polycrystalline substrate is less than an RF absorption coefficient of a silicon substrate.

12. The substrate structure of claim 1 wherein an electrical resistivity of the polycrystalline substrate is greater than about 10¹⁴ ohm-cm.

13. A method of fabricating a substrate structure, the method comprising:

forming a support structure by;

providing a polycrystalline substrate; and

forming a plurality of thin film layers on the polycrystalline substrate;

forming a bonding layer coupled to at least a portion of the plurality of thin film layers; and

joining a single crystal silicon layer to the bonding layer.

14. The method of claim 13 further comprising forming a plurality of laterally diffused MOSFET (LDMOS) devices coupled to the single crystal silicon layer.

15. The method of claim 13 wherein joining the single crystal silicon layer comprises performing a layer transfer process from a silicon wafer having a (100) crystalline orientation.

16. The method of claim 13 wherein the polycrystalline substrate comprises polycrystalline aluminum nitride.

17. The method of claim 16 wherein forming the plurality of thin film layers comprises:

encapsulating the polycrystalline substrate in an adhesion shell; and

encapsulating the adhesion shell in a barrier material.

18. The method of claim 17 wherein:

the adhesion shell comprises tetraethyl orthosilicate (TEOS); and

the barrier material comprises silicon nitride.

19. The method of claim 13 wherein the bonding layer comprises silicon oxide and has a thickness of 1 μ

m or less, 300 nm or less, 100 nm or less, or 30 nm or less.

20. A device structure comprising:

a support structure comprising;

a polycrystalline ceramic core;

a first adhesion layer coupled to the polycrystalline ceramic core;

a conductive layer coupled to the first adhesion layer;

a second adhesion layer coupled to the conductive layer; and

a barrier layer coupled to the second adhesion layer;

a silicon oxide layer coupled to the support structure;

a single crystal silicon layer coupled to the silicon oxide layer; and

a plurality of laterally diffused MOSFET (LDMOS) devices coupled to the single crystal silicon layer.

21. The device structure of claim 20 wherein the polycrystalline ceramic core comprises polycrystalline aluminum nitride.

22. The device structure of claim 21 wherein the single crystal silicon layer has a (100) crystalline orientation.

23. The device structure of claim 21 wherein the silicon oxide layer has a thickness of 1 μ

m or less, 300 nm or less, 100 nm or less, or 30 nm or less.

24. The device structure of claim 21 wherein:

the first adhesion layer comprises a first tetraethyl orthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core;

the conductive layer comprises a polysilicon layer encapsulating the first TEOS layer;

the second adhesion layer comprises a second TEOS layer encapsulating the polysilicon layer; and

the barrier layer comprises a silicon nitride layer encapsulating the second TEOS layer.