Trenched MOS Gate Controlled Rectifier

• US 20170288065A1
• Filed: 04/01/2016
• Published: 10/05/2017
• Est. Priority Date: 04/01/2016
• Status: Active Grant

• Current Assignee: Diodes Incorporated
• Original Assignee: Diodes Incorporated
• Inventors: Blair, Peter Hugh, Riley, Lee Spencer
• Granted Patent: US 10,854,759 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes

Abstract

A trenched MOS gate controlled rectifier has an asymmetric trench structure between the active area of active trenches and the termination area of termination trenches. The asymmetric trench structure has a gate electrode on one side of the trench to turn on and off the channel of the MOS structure effectively and a field plate structure on the other side with field dielectric sufficiently thick in order to sustain the high electric field during the reverse bias condition.

Claims

1. A semiconductor chip, comprising

a trench structure, comprising;

a first trench with opening at a top surface of the chip having sidewalls of a epitaxial semiconductor material;

a second trench in the middle of the first trench, with opening at near the top surface, having sidewalls of dielectric material, and filled with a field plate; and

the field plate having adjacent gate electrode on one side and free of adjacent gate electrode on the opposite side.

2. The semiconductor chip of claim 1, in which the gate electrode is separated from the sidewall of the epitaxial semiconductor material by a first dielectric layer of a first thickness and separated from the field plate by a second dielectric layer of a different thickness from the first thickness.

3. The semiconductor of the claim 2, in which the gate electrode and the field plate are connected by a conductive layer at near the top surface of the chip.

4. The semiconductor of claim 1, further comprising a first symmetric trench and a second symmetric trench structure.

5. The semiconductor chip of claim 4, in which the first symmetric trench has two gate electrodes adjacent to sidewalls of the first symmetric trench.

6. The semiconductor chip of claim 5, in which the second symmetric trench has no gate electrode.

7. The semiconductor chip of claim 6, in which the one gate electrode in asymmetric trench is separated from a sidewall of the epitaxial semiconductor material by a gate dielectric.

8. The semiconductor chip of claim 7, further comprising a first mesa separating the asymmetric trench from the first symmetric trench and a second mesa separating the asymmetric trench from the second symmetric trench.

9. The semiconductor chip of claim 8, in which a conductive layer connects the first mesa at the top surface of the chip and the field plate but does not connect the second mesa at the top surface of the chip.

10. A process of making an asymmetric trench in a semiconductor chip, comprising:

lining sidewalls of a trench in the chip with a dielectric layer;

covering the dielectric layer on one sidewall and exposing the dielectric layer on the opposite sidewall; and

removing portion of the exposed dielectric layer.

11. A semiconductor device, comprising:

a semiconductor chip having an asymmetric trench structure, comprising;

a first trench having semiconductor sidewalls;

a second trench having dielectric sidewalls and disposed inside the first trench; and

a third trench having dielectric sidewalls and disposed inside the first trench and outside the second trench.

12. The semiconductor device of claim 11, in which the first trench has an opening at a top surface of the semiconductor chip;

and a first sidewall near the opening is lined with a first layer of dielectric layer and a second sidewall opposite the first sidewall near the opening is lined with a second layer of dielectric layer, which is more than ten times thicker than the first layer of dielectric layer.

13. The semiconductor device in claim 12, in which the second trench has an opening at the top surface of the semiconductor chip and is filled with a conductive material extending above the top surface.

14. The semiconductor device of claim 13, in which the third trench and the second trench are filled with conductive material;

and a conductive layer connects the conductive material in the second trench and the third trench near the top surface.

15. The semiconductor device of claim 14, in which a portion of the conductive material is not connected to the conductive layer near the top surface.

16. The semiconductor device of claim 15, in which the conductive layer further connects the top surface of the chip.

17. The semiconductor of claim 11, further comprising a first symmetric trench structure and a second symmetric trench structure adjacent to the asymmetric trench structure.

18. The semiconductor device of claim 17, in which the first symmetric trench structure comprises a plurality of trenches, and the second symmetric trench structure comprises a plurality of trenches.

19. The semiconductor device of claim 18, in which the plurality of trenches of the second symmetric trench structure encloses, at the top surface of the chip, the asymmetric trench structure and the plurality of the trenches of the first symmetric trenches.

20. The semiconductor device of claim 19, in which the plurality of trenches of the first symmetric trench structure and the plurality of trenches of the second symmetric trench structure have field plates;

and a conductive layer connects all field plates of the first symmetric trench structure but not all the field plates of the second symmetric trench structure.

21. The semiconductor device of claim 20, further comprising gate electrodes in the plurality of trenches of the first symmetric trench structure, connected by the conductive layer.